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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A805.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5984 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Rafal Ostrowski [Why] - The builder passed a NULL is_ungated, so these steps never programmed under BLS: DSC_WAIT_DISCONNECT_PENDING_CLEAR, DSC_DISABLE, DCCG_SET_REF_DSCCLK. The immediate path does program them. [How] - Store the DSC_PG_STATUS result in the new dsc->pg_ungated; the three steps read it at execute time. - Pass the DSC pointer to the four adders instead of dsc_inst and is_ungated. - hwss_add_dsc_pg_status returns whether it emitted a step; if not, the builder emits no dependent steps. - Adders validate their arguments and hooks; executors only program. Cc: Alvin Lee Signed-off-by: Rafal Ostrowski Signed-off-by: Wayne Lin --- .../drm/amd/display/dc/core/dc_hw_sequencer.c | 81 +++++++++---------- drivers/gpu/drm/amd/display/dc/dc_dsc.h | 1 + .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 20 +++-- .../amd/display/dc/hwss/dcn60/dcn60_hwseq.c | 9 +++ .../amd/display/dc/hwss/dcn60/dcn60_hwseq.h | 1 + .../amd/display/dc/hwss/dcn60/dcn60_init.c | 2 +- .../drm/amd/display/dc/hwss/hw_sequencer.h | 22 ++--- 7 files changed, 66 insertions(+), 70 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c index 32a33d29835e..c5e8a88d051d 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c @@ -4033,22 +4033,16 @@ void hwss_disable_phantom_crtc(union block_sequence_params *params) void hwss_dsc_pg_status(union block_sequence_params *params) { struct dce_hwseq *hws = params->dsc_pg_status_params.hws; - int dsc_inst = params->dsc_pg_status_params.dsc_inst; + struct display_stream_compressor *dsc = params->dsc_pg_status_params.dsc; - if (hws && hws->funcs.dsc_pg_status) - params->dsc_pg_status_params.is_ungated = hws->funcs.dsc_pg_status(hws, dsc_inst); + dsc->pg_ungated = hws->funcs.dsc_pg_status(hws, dsc->inst); } void hwss_dsc_wait_disconnect_pending_clear(union block_sequence_params *params) { struct display_stream_compressor *dsc = params->dsc_wait_disconnect_pending_clear_params.dsc; - if (!params->dsc_wait_disconnect_pending_clear_params.is_ungated) - return; - if (*params->dsc_wait_disconnect_pending_clear_params.is_ungated == false) - return; - - if (dsc && dsc->funcs->dsc_wait_disconnect_pending_clear) + if (dsc->pg_ungated) dsc->funcs->dsc_wait_disconnect_pending_clear(dsc); } @@ -4056,27 +4050,17 @@ void hwss_dsc_disable(union block_sequence_params *params) { struct display_stream_compressor *dsc = params->dsc_disable_params.dsc; - if (!params->dsc_disable_params.is_ungated) - return; - if (*params->dsc_disable_params.is_ungated == false) - return; - - if (dsc && dsc->funcs->dsc_disable) + if (dsc->pg_ungated) dsc->funcs->dsc_disable(dsc); } void hwss_dccg_set_ref_dscclk(union block_sequence_params *params) { struct dccg *dccg = params->dccg_set_ref_dscclk_params.dccg; - int dsc_inst = params->dccg_set_ref_dscclk_params.dsc_inst; - - if (!params->dccg_set_ref_dscclk_params.is_ungated) - return; - if (*params->dccg_set_ref_dscclk_params.is_ungated == false) - return; + const struct display_stream_compressor *dsc = params->dccg_set_ref_dscclk_params.dsc; - if (dccg && dccg->funcs->set_ref_dscclk) - dccg->funcs->set_ref_dscclk(dccg, dsc_inst); + if (dsc->pg_ungated) + dccg->funcs->set_ref_dscclk(dccg, dsc->inst); } void hwss_dpp_pg_control(union block_sequence_params *params) @@ -5457,54 +5441,65 @@ void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state, } } -void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state, +bool hwss_add_dsc_pg_status(struct block_sequence_state *seq_state, struct dce_hwseq *hws, - int dsc_inst, - bool is_ungated) + struct display_stream_compressor *dsc) { - if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { - seq_state->steps[*seq_state->num_steps].func = DSC_PG_STATUS; - seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.hws = hws; - seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.dsc_inst = dsc_inst; - seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.is_ungated = is_ungated; - (*seq_state->num_steps)++; - } + if (!seq_state || !seq_state->steps || !seq_state->num_steps || + !hws || !hws->funcs.dsc_pg_status || !dsc) + return false; + + if (*seq_state->num_steps >= MAX_HWSS_BLOCK_SEQUENCE_SIZE) + return false; + + seq_state->steps[*seq_state->num_steps].func = DSC_PG_STATUS; + seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.hws = hws; + seq_state->steps[*seq_state->num_steps].params.dsc_pg_status_params.dsc = dsc; + (*seq_state->num_steps)++; + + return true; } void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state, - struct display_stream_compressor *dsc, - bool *is_ungated) + struct display_stream_compressor *dsc) { + if (!seq_state || !seq_state->steps || !seq_state->num_steps || + !dsc || !dsc->funcs || !dsc->funcs->dsc_wait_disconnect_pending_clear) + return; + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { seq_state->steps[*seq_state->num_steps].func = DSC_WAIT_DISCONNECT_PENDING_CLEAR; seq_state->steps[*seq_state->num_steps].params.dsc_wait_disconnect_pending_clear_params.dsc = dsc; - seq_state->steps[*seq_state->num_steps].params.dsc_wait_disconnect_pending_clear_params.is_ungated = is_ungated; (*seq_state->num_steps)++; } } void hwss_add_dsc_disable(struct block_sequence_state *seq_state, - struct display_stream_compressor *dsc, - bool *is_ungated) + struct display_stream_compressor *dsc) { + if (!seq_state || !seq_state->steps || !seq_state->num_steps || + !dsc || !dsc->funcs || !dsc->funcs->dsc_disable) + return; + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { seq_state->steps[*seq_state->num_steps].func = DSC_DISABLE; seq_state->steps[*seq_state->num_steps].params.dsc_disable_params.dsc = dsc; - seq_state->steps[*seq_state->num_steps].params.dsc_disable_params.is_ungated = is_ungated; (*seq_state->num_steps)++; } } void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state, struct dccg *dccg, - int dsc_inst, - bool *is_ungated) + const struct display_stream_compressor *dsc) { + if (!seq_state || !seq_state->steps || !seq_state->num_steps || + !dccg || !dccg->funcs || !dccg->funcs->set_ref_dscclk || !dsc) + return; + if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) { seq_state->steps[*seq_state->num_steps].func = DCCG_SET_REF_DSCCLK; seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dccg = dccg; - seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dsc_inst = dsc_inst; - seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.is_ungated = is_ungated; + seq_state->steps[*seq_state->num_steps].params.dccg_set_ref_dscclk_params.dsc = dsc; (*seq_state->num_steps)++; } } diff --git a/drivers/gpu/drm/amd/display/dc/dc_dsc.h b/drivers/gpu/drm/amd/display/dc/dc_dsc.h index de169ed3b3b7..99592d5bb3c4 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_dsc.h +++ b/drivers/gpu/drm/amd/display/dc/dc_dsc.h @@ -43,6 +43,7 @@ struct display_stream_compressor { const struct dsc_funcs *funcs; struct dc_context *ctx; int inst; + bool pg_ungated; }; struct dc_dsc_policy { diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index f14cba867111..cc78b4794cef 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -1828,7 +1828,8 @@ static void dcn401_add_dsc_sequence_for_odm_change(struct dc *dc, struct dc_stat if (otg_master->stream_res.dsc && otg_master->stream->timing.flags.DSC) { if (!hwss_add_dsc_sequence_for_stream(seq_state, otg_master, otg_master->dsc_padding_params.dsc_hactive_padding, NULL)) { - ASSERT(false); + /* DSC sequence is deliberately skipped while the stream is dpms off */ + ASSERT(otg_master->stream->dpms_off); return; } } else if (otg_master->stream_res.dsc && !otg_master->stream->timing.flags.DSC) { @@ -3635,12 +3636,10 @@ void dcn401_post_unlock_reset_opp_sequence( if (dc->hwss.wait_for_mpcc_disconnect_sequence) dc->hwss.wait_for_mpcc_disconnect_sequence(dc, dc->res_pool, opp_head, seq_state); - if (dsc) { - bool *is_ungated = NULL; - /* Check DSC power gate status */ - if (dc->hwseq && dc->hwseq->funcs.dsc_pg_status) - hwss_add_dsc_pg_status(seq_state, dc->hwseq, dsc->inst, false); - + /* Check DSC power gate status; the result is kept in dsc->pg_ungated and + * gates the steps below at execute time. + */ + if (dsc && hwss_add_dsc_pg_status(seq_state, dc->hwseq, dsc)) { /* Seamless update specific where we will postpone non * double buffered DSCCLK disable logic in post unlock * sequence after DSC is disconnected from OPP but not @@ -3648,14 +3647,13 @@ void dcn401_post_unlock_reset_opp_sequence( */ /* DSC wait disconnect pending clear */ - hwss_add_dsc_wait_disconnect_pending_clear(seq_state, dsc, is_ungated); + hwss_add_dsc_wait_disconnect_pending_clear(seq_state, dsc); /* DSC disable */ - hwss_add_dsc_disable(seq_state, dsc, is_ungated); + hwss_add_dsc_disable(seq_state, dsc); /* Set reference DSCCLK */ - if (dccg && dccg->funcs->set_ref_dscclk) - hwss_add_dccg_set_ref_dscclk(seq_state, dccg, dsc->inst, 0); + hwss_add_dccg_set_ref_dscclk(seq_state, dccg, dsc); } } diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c index f8254dfe1ce7..8a38b7f0bef0 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.c @@ -1332,3 +1332,12 @@ bool dcn60_apply_idle_power_optimizations(struct dc *dc, bool enable) return true; } + +bool dcn60_dsc_pg_status(struct dce_hwseq *hws, unsigned int dsc_inst) +{ + (void)hws; + (void)dsc_inst; + + /* DCN6.0 has no DSC power-gate domain, so the DSC is always ungated. */ + return true; +} diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h index b880988ff1fc..b88f4304b1b9 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_hwseq.h @@ -29,6 +29,7 @@ void dcn60_update_cursor_offload_pipe(struct dmub_srv *dmub, uint32_t stream_idx void dcn60_program_perfmon(struct dc *dc, struct dc_state *context); bool dcn60_apply_idle_power_optimizations(struct dc *dc, bool enable); +bool dcn60_dsc_pg_status(struct dce_hwseq *hws, unsigned int dsc_inst); bool dcn60_set_rmcm_luts(struct set_input_transfer_func_params *params); diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c index 9fde7d1be3e5..d5c8dcc86a9f 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn60/dcn60_init.c @@ -159,7 +159,7 @@ static const struct hwseq_private_funcs dcn60_private_funcs = { .update_odm = dcn401_update_odm, .update_odm_sequence = dcn401_update_odm_sequence, .dsc_pg_control = NULL, - .dsc_pg_status = NULL, + .dsc_pg_status = dcn60_dsc_pg_status, .set_hdr_multiplier = dcn10_set_hdr_multiplier, .set_hdr_multiplier_sequence = dcn401_set_hdr_multiplier_sequence, .wait_for_blank_complete = dcn20_wait_for_blank_complete, diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h index 6996ce12a17d..c4f3ec532572 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h +++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h @@ -1037,24 +1037,20 @@ struct dc_ip_request_cntl_params { struct dsc_pg_status_params { struct dce_hwseq *hws; - int dsc_inst; - bool is_ungated; + struct display_stream_compressor *dsc; }; struct dsc_wait_disconnect_pending_clear_params { struct display_stream_compressor *dsc; - bool *is_ungated; }; struct dsc_disable_params { struct display_stream_compressor *dsc; - bool *is_ungated; }; struct dccg_set_ref_dscclk_params { struct dccg *dccg; - int dsc_inst; - bool *is_ungated; + const struct display_stream_compressor *dsc; }; struct dccg_update_dpp_dto_params { @@ -2919,23 +2915,19 @@ void hwss_add_dpp_dppclk_control(struct block_sequence_state *seq_state, void hwss_add_disable_phantom_crtc(struct block_sequence_state *seq_state, struct timing_generator *tg); -void hwss_add_dsc_pg_status(struct block_sequence_state *seq_state, +bool hwss_add_dsc_pg_status(struct block_sequence_state *seq_state, struct dce_hwseq *hws, - int dsc_inst, - bool is_ungated); + struct display_stream_compressor *dsc); void hwss_add_dsc_wait_disconnect_pending_clear(struct block_sequence_state *seq_state, - struct display_stream_compressor *dsc, - bool *is_ungated); + struct display_stream_compressor *dsc); void hwss_add_dsc_disable(struct block_sequence_state *seq_state, - struct display_stream_compressor *dsc, - bool *is_ungated); + struct display_stream_compressor *dsc); void hwss_add_dccg_set_ref_dscclk(struct block_sequence_state *seq_state, struct dccg *dccg, - int dsc_inst, - bool *is_ungated); + const struct display_stream_compressor *dsc); bool hwss_is_dpp_root_clock_control_allowed(struct dce_hwseq *hws, bool clock_on); -- 2.43.0