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Tue, 10 Nov 2026 19:43:08 -0600 From: Wayne Lin To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Taimur Hassan Subject: [PATCH 43/74] drm/amd/display: Promote DC to 3.2.406 Date: Wed, 11 Nov 2026 09:28:49 +0800 Message-ID: <20261111014100.3596072-44-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261111014100.3596072-1-Wayne.Lin@amd.com> References: <20261111014100.3596072-1-Wayne.Lin@amd.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF00000209:EE_|DS6PR12MB934327:EE_ X-MS-Office365-Filtering-Correlation-Id: 5708cd2f-64e4-405f-adfa-08df3f9525c5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|82310400026|23010399003|1800799024|36860700016|261009223027099003|10067099003|3023799007|261028144727099003|261102123227099003|261026140227099003|261026121527099003|261021123027099003|261021121427099003|261022105027099003|56012099006|11063799006|22082099003|18002099003; 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Raise the DCN42 DDR5 stutter latency. - Let DC_PSR_MASK enable PSR without a DMUB PSR cap. - Enable HDCP on DCN6 and the DF C-state vote on DCN42B. - Enable SST PCON FRL DSC passthrough and program the correct DP HPO APG instance. - Exit IPS before checking flip pending, and keep the HPD IRQ reset path from taking dc_lock. - Skip UPSP programming when the registers are absent, and skip visual confirm color programming when firmware owns it. - Align DCN42B with DCN42 and extend the IOMMU mismatch workaround to DCN42B. Restore the missing DCN6 vtotal cap and vstartup assignment. - Update the DMUB interface to 0.1.83.0 with an extended SoC bounding box, RAMLESS_LOBF commands, and a seamless-boot eDP request. - Initialize the DMUB LSDMA ring, accept a 1932-byte PSP footer, and update the default VCO frequency. - Fix the FFE link-rate change path and the p-state enable sequence. Commit the validated target when a minimal transition cannot be built. - Various cleanups. Signed-off-by: Taimur Hassan Signed-off-by: Wayne Lin --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 916fa87d0dbc..2dff1b271416 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -69,7 +69,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.405" +#define DC_VER "3.2.406" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC -- 2.43.0