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Tue, 10 Nov 2026 19:43:27 -0600 From: Wayne Lin To: CC: Harry Wentland , Leo Li , Aurabindo Pillai , Roman Li , Wayne Lin , Tom Chung , "Fangzhi Zuo" , Dan Wheeler , Ray Wu , Ivan Lipski , Alex Hung , James Lin , Chenyu Chen , Charlene Liu , Chris Park Subject: [PATCH 48/74] drm/amd/display: Keep patched HDMI panels on FRL across detect Date: Wed, 11 Nov 2026 09:28:54 +0800 Message-ID: <20261111014100.3596072-49-Wayne.Lin@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261111014100.3596072-1-Wayne.Lin@amd.com> References: <20261111014100.3596072-1-Wayne.Lin@amd.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: EA8PEPF0000000A:EE_|BL1PR12MB5993:EE_ X-MS-Office365-Filtering-Correlation-Id: ae2c348a-eb3a-4825-c776-08df3f95312b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700016|23010399003|1800799024|376014|82310400026|261009223027099003|10067099003|261028144727099003|3023799007|261102123227099003|261021121427099003|261022075727099003|261022105027099003|261021123027099003|261026121527099003|261026140227099003|56012099006|11063799006|5023799004|22082099003|18002099003; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sgyqRc9oyMCrTYF5nB0O2iGbYexVYzfhk35OrvY6pw2fnGb3vYTzJLiKZmuVEl+a34DtCMpEgcMcCBykor6qeWcVghHB0BA2DZlGlkPS3TXQW9gdZyIz74b32rLw/7lhQiJG+Jj78bA9yVo5eS/NyqAdYVLKCY5h98iX4ThKpE8QIOapDUeTUb6lf8wFd2vuauDtBowz14A+/nsCa36+2G7S26wArpq+KvmxeBy4zaEruBnU9FVwdfidLwlQ0r5vUYo1U7QYBC2B+VqpJtDMF7TQRA5F7NmvUdtziy5LOj4DfqCm2vLcE200YqLvo0oi0FVay3xafLJyFL9VbHsi0v93TvGdiYRva3sIzr60iriguuozcK1OZa7VQruFchy/WlEGsXc+QaYsbCSwFXgxk3SCDzuCo4F556k606ZMybiWGj96zMtZ6eWl7HUrE4bX X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Nov 2026 01:43:31.6182 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ae2c348a-eb3a-4825-c776-08df3f95312b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: EA8PEPF0000000A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL1PR12MB5993 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Charlene Liu [Why] A patched panel sets force_frl so update_stream_signal() keeps an FRL stream instead of dropping it to TMDS. The flags stay on the link, so a later sink with no FRL rate can keep the previous panel's force_frl_always. Setting the flag on an encoder that cannot drive FRL also picks a signal the ASIC cannot output. [How] verify_link_capability() sets force_frl_always, force_frl_max and force_frl_dsc from the current panel patch when the encoder is FRL capable and max_frl_rate is non-zero. It does not clear a flag the patch leaves unset. Otherwise it clears those three flags. hdmi_frl_verify_link_cap() applies force_frl only when the encoder is FRL capable. Cc: Chris Park Signed-off-by: Charlene Liu Signed-off-by: Wayne Lin --- .../drm/amd/display/dc/link/link_detection.c | 26 +++++++++++++++++++ .../display/dc/link/protocols/link_hdmi_frl.c | 7 ++++- 2 files changed, 32 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c index b4546f93af0c..5b257f003f13 100644 --- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c +++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c @@ -1006,6 +1006,32 @@ static bool should_verify_link_capability_destructively(struct dc_link *link, static void verify_link_capability(struct dc_link *link, enum dc_detect_reason reason) { + /* The FRL force flags are only fully recomputed on the destructive path + * (hdmi_frl_verify_link_cap), so re-derive the sink driven part on every + * detect. Without this a sink can either inherit flags from a previously + * connected monitor, or stay cleared when a patched monitor is detected + * through one of the non destructive paths (FRL already in use, + * skip_frl_pre_training on an active link, or skip_detection_link_training). + * Setting them is additive so SCDC test request results survive, and the + * destructive path overwrites all of them anyway. + */ + if (link->link_enc && + link->link_enc->features.flags.bits.IS_HDMI_FRL_CAPABLE && + link->local_sink && + link->local_sink->edid_caps.max_frl_rate != 0) { + if (link->local_sink->edid_caps.panel_patch.force_frl) + link->frl_flags.force_frl_always = true; + + if (link->local_sink->edid_caps.panel_patch.hdmi_comp_auto) { + link->frl_flags.force_frl_max = true; + link->frl_flags.force_frl_dsc = true; + } + } else { + link->frl_flags.force_frl_always = false; + link->frl_flags.force_frl_max = false; + link->frl_flags.force_frl_dsc = false; + } + if (should_verify_link_capability_destructively(link, reason)) verify_link_capability_destructive(link, reason); else diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c index c31be4900e8d..3f687603a70c 100644 --- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c +++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_hdmi_frl.c @@ -902,8 +902,13 @@ void hdmi_frl_verify_link_cap(struct dc_link *link, if (link->frl_flags.force_frl_rate == 0xF) return; + /* Only honour the force FRL monitor patch when VBIOS reports the encoder + * as FRL capable, otherwise the stream would be forced to a signal type + * the ASIC cannot drive. + */ if (link->local_sink && - link->local_sink->edid_caps.panel_patch.force_frl) + link->local_sink->edid_caps.panel_patch.force_frl && + link->link_enc->features.flags.bits.IS_HDMI_FRL_CAPABLE) link->frl_flags.force_frl_always = true; if (!link->frl_flags.force_frl_max && -- 2.43.0