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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: EA8PEPF00000006.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8793 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Ovidiu Bunea [Why] When the first plane is enabled, P-State is forced to block UCLK switching while the new HUBP is brought up. This is only needed when the HUBP MIN_TTU_VBLANK is below UCLK_PSTATE_CHANGE_WATERMARK_A. Otherwise the force is unnecessary and adds a 500us delay. [How] Track the smallest MIN_TTU_VBLANK across the new pipes and compare it against watermark A. prepare_bandwidth only raises watermarks, so HW holds the max of the old and new values; compare against that. Only force P-State and wait when MIN_TTU_VBLANK is below the watermark. Cc: Dillon Varone Signed-off-by: Ovidiu Bunea Signed-off-by: Wayne Lin --- .../amd/display/dc/hwss/dcn401/dcn401_hwseq.c | 25 +++++++++++++++---- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c index cc78b4794cef..bac9c5e18e6a 100644 --- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c +++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c @@ -2591,6 +2591,7 @@ void dcn401_program_front_end_for_ctx( unsigned int i; unsigned int prev_hubp_count = 0; unsigned int hubp_count = 0; + unsigned int min_ttu_vblank = UINT_MAX; struct dce_hwseq *hws = dc->hwseq; struct pipe_ctx *pipe = NULL; @@ -2623,17 +2624,31 @@ void dcn401_program_front_end_for_ctx( } for (i = 0; i < dc->res_pool->pipe_count; i++) { + pipe = &context->res_ctx.pipe_ctx[i]; + if (dc->current_state->res_ctx.pipe_ctx[i].plane_state) prev_hubp_count++; - if (context->res_ctx.pipe_ctx[i].plane_state) + if (pipe->plane_state) { hubp_count++; + min_ttu_vblank = min(min_ttu_vblank, + pipe->hubp_regs.ttu_regs.min_ttu_vblank); + } } if (prev_hubp_count == 0 && hubp_count > 0) { - if (dc->res_pool->hubbub->funcs->force_pstate_change_control) - dc->res_pool->hubbub->funcs->force_pstate_change_control( - dc->res_pool->hubbub, true, false); - udelay(500); + struct hubbub *hubbub = dc->res_pool->hubbub; + unsigned int pstate_wm_a; + + /* WM_A is only raised in prepare_bandwidth, so HW holds the max of old and new */ + pstate_wm_a = max(context->bw_ctx.bw.dcn.watermarks.dcn4x.a.uclk_pstate, + dc->current_state->bw_ctx.bw.dcn.watermarks.dcn4x.a.uclk_pstate); + + /* MIN_TTU_VBLANK and UCLK_PSTATE_CHANGE_WATERMARK_A are both in refclk cycles */ + if (min_ttu_vblank < pstate_wm_a) { + if (hubbub->funcs->force_pstate_change_control) + hubbub->funcs->force_pstate_change_control(hubbub, true, false); + udelay(500); + } } /* Set pipe update flags and lock pipes */ -- 2.43.0