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Ip=[165.204.84.17]; Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: EA8PEPF00000005.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LY0PR12MB888806 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Ashwin Santhosh [Why] When a plane is split across pipes (ODM or MPC), each pipe's viewport extends past its even share: scaler taps at the split, the leftover of an uneven split, and the 4:2:x left edge pixel under ODM. DML sized the per-pipe swath width and the alt channel copy region without these, so with 8K VSR on a 4K240 panel (ODM 2:1, 6 taps) each pipe's copy was one tile column too small and overran the next pipe's region, showing as blocks of corruption during MCLK switches. [How] Add calculate_per_pipe_swath_width to pad the ODM and MPC swath widths by these extra pixels, and size the alt channel copy from the swath width for all pipe configs. Cc: Dillon Varone Signed-off-by: Ashwin Santhosh Signed-off-by: Wayne Lin --- .../dml2_core/dml2_core_dcn5_calcs_dchub.c | 67 ++++++++++++++----- .../dml2_core/dml2_core_dcn6_calcs_dchub.c | 26 ++----- 2 files changed, 57 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c index 569ab02ea080..9c1f66c18a19 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn5_calcs_dchub.c @@ -242,6 +242,51 @@ void dcn5_calculate_byte_per_pixel_and_block_sizes( DML_LOG_VERBOSE("DML::%s: MacroTileHeightC = %u\n", __func__, *MacroTileHeightC); } +/* + * calculate_per_pipe_swath_width: Swath width of one pipe, accounting for the plane being split across pipes + * (ODM or MPC combine) + * + * Each pipe's viewport extends past its even share of the split: + * - max_recout_pixels: the widest recout (screen / dst pixels) any pipe of the split can get + * - h_taps: the scaler taps sampling past the split, already counted in surface (src) pixels + * h_ratio converts the recout into src pixels, since the swath is fetched from the surface. + */ +static unsigned int calculate_per_pipe_swath_width(const struct dml2_plane_parameters *plane, + const struct dml2_stream_parameters *stream, enum dml2_odm_mode odm_mode, unsigned int dpp_per_surface, + unsigned int single_dpp_swath_width, bool chroma) +{ + double h_ratio = chroma ? plane->composition.scaler_info.plane1.h_ratio : plane->composition.scaler_info.plane0.h_ratio; + unsigned int h_taps = chroma ? plane->composition.scaler_info.plane1.h_taps : plane->composition.scaler_info.plane0.h_taps; + unsigned int odm_factor; + double max_recout_pixels; + unsigned int swath_width; + + if (odm_mode == dml2_odm_mode_combine_4to1) + odm_factor = 4; + else if (odm_mode == dml2_odm_mode_combine_3to1) + odm_factor = 3; + else if (odm_mode == dml2_odm_mode_combine_2to1) + odm_factor = 2; + else + odm_factor = 1; + + if (odm_factor > 1) { + // h_active may not split evenly across ODM pipes. The last pipe takes the leftover, which is at most odm - 1 pixels + max_recout_pixels = (double)stream->timing.h_active / odm_factor + (odm_factor - 1); + // 4:2:0 / 4:2:2 outputs add a left edge pixel for the chroma subsampling filter + if (stream->output.output_format == dml2_420 || stream->output.output_format == dml2_s422 || stream->output.output_format == dml2_n422) + max_recout_pixels += 1; + swath_width = (unsigned int)math_ceil(max_recout_pixels * h_ratio) + h_taps; + } else if (dpp_per_surface == 2) { + // MPC splits the plane in half, with the leftover pixel of an odd width going to one pipe + swath_width = (single_dpp_swath_width + 1) / 2 + h_taps; + } else { + swath_width = single_dpp_swath_width; + } + + return (unsigned int)math_min2((double)single_dpp_swath_width, (double)swath_width); +} + void dcn5_calculate_swath_width( const struct dml2_display_cfg *display_cfg, bool ForceSingleDPP, @@ -273,7 +318,6 @@ void dcn5_calculate_swath_width( { (void)BytePerPixY; enum dml2_odm_mode MainSurfaceODMMode; - double odm_hactive_factor = 1.0; unsigned int req_width_horz_y; unsigned int req_width_horz_c; unsigned int surface_width_ub_l; @@ -285,6 +329,9 @@ void dcn5_calculate_swath_width( DML_LOG_VERBOSE("DML::%s: NumberOfActiveSurfaces = %u\n", __func__, NumberOfActiveSurfaces); for (unsigned int k = 0; k < NumberOfActiveSurfaces; ++k) { + const struct dml2_plane_parameters *plane = &display_cfg->plane_descriptors[k]; + const struct dml2_stream_parameters *stream = &display_cfg->stream_descriptors[plane->stream_index]; + if (!dml2_core_utils_is_vertical_rotation(display_cfg->plane_descriptors[k].composition.rotation_angle)) { SwathWidthSingleDPPY[k] = (unsigned int)display_cfg->plane_descriptors[k].composition.viewport.plane0.width; } else { @@ -300,20 +347,7 @@ void dcn5_calculate_swath_width( if (ForceSingleDPP) { SwathWidthY[k] = SwathWidthSingleDPPY[k]; } else { - if (MainSurfaceODMMode == dml2_odm_mode_combine_4to1) - odm_hactive_factor = 4.0; - else if (MainSurfaceODMMode == dml2_odm_mode_combine_3to1) - odm_hactive_factor = 3.0; - else if (MainSurfaceODMMode == dml2_odm_mode_combine_2to1) - odm_hactive_factor = 2.0; - - if (MainSurfaceODMMode == dml2_odm_mode_combine_4to1 || MainSurfaceODMMode == dml2_odm_mode_combine_3to1 || MainSurfaceODMMode == dml2_odm_mode_combine_2to1) { - SwathWidthY[k] = (unsigned int)(math_min2((double)SwathWidthSingleDPPY[k], math_round((double)display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active / odm_hactive_factor * display_cfg->plane_descriptors[k].composition.scaler_info.plane0.h_ratio))); - } else if (DPPPerSurface[k] == 2) { - SwathWidthY[k] = SwathWidthSingleDPPY[k] / 2; - } else { - SwathWidthY[k] = SwathWidthSingleDPPY[k]; - } + SwathWidthY[k] = calculate_per_pipe_swath_width(plane, stream, MainSurfaceODMMode, DPPPerSurface[k], SwathWidthSingleDPPY[k], false); } DML_LOG_VERBOSE("DML::%s: k=%u HActive=%lu\n", __func__, k, display_cfg->stream_descriptors[display_cfg->plane_descriptors[k].stream_index].timing.h_active); @@ -323,8 +357,9 @@ void dcn5_calculate_swath_width( DML_LOG_VERBOSE("DML::%s: k=%u SwathWidthY=%u\n", __func__, k, SwathWidthY[k]); if (dml2_core_utils_is_420(display_cfg->plane_descriptors[k].pixel_format) || dml2_core_utils_is_422_planar(display_cfg->plane_descriptors[k].pixel_format)) { - SwathWidthC[k] = SwathWidthY[k] / 2; SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k] / 2; + // Chroma taps apply at the chroma ratio, so the padded luma width can't simply be halved + SwathWidthC[k] = calculate_per_pipe_swath_width(plane, stream, MainSurfaceODMMode, DPPPerSurface[k], SwathWidthSingleDPPC[k], true); } else { SwathWidthC[k] = SwathWidthY[k]; SwathWidthSingleDPPC[k] = SwathWidthSingleDPPY[k]; diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c index a61a1037bb73..2ee50f8cf2f5 100644 --- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c +++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_dcn6_calcs_dchub.c @@ -227,43 +227,29 @@ static unsigned int calculate_tile_aligned_size(unsigned int copy_width, unsigne * ******************************************************************************************************************************************************* * calculate_max_mem_size_per_plane_per_dpp: Calculate (loose) upper bound for total number of bytes reserved in memory for the copy given number of swaths * - * - The copy width / height is the min of the vp_width/height and maximum number of pixels that can fit across an ODM slice - * - This is to account for recout positions that cross the ODM seam but are "mostly" within the same ODM slice + * - The copy width / height is the min of the vp_width/height and the per-pipe swath width + * - This is to account for recout positions that cross the ODM / MPC split but are "mostly" within the same pipe * * ******************************************************************************************************************************************************* */ static unsigned int calculate_max_mem_size_per_plane_per_dpp(const struct dml2_core_calcs_calculate_alternate_params *p, unsigned int plane_idx, unsigned int copy_swaths, bool chroma) { bool vertical_access = p->display_cfg->plane_descriptors[plane_idx].composition.rotation_angle == dml2_rotation_90 || p->display_cfg->plane_descriptors[plane_idx].composition.rotation_angle == dml2_rotation_270; - unsigned int h_active = p->display_cfg->stream_descriptors[p->display_cfg->plane_descriptors[plane_idx].stream_index].timing.h_active; - double h_ratio = chroma ? p->display_cfg->plane_descriptors[plane_idx].composition.scaler_info.plane1.h_ratio : p->display_cfg->plane_descriptors[plane_idx].composition.scaler_info.plane0.h_ratio; unsigned int copy_src_lines = copy_swaths * (chroma ? p->SwathHeightC[plane_idx] : p->SwathHeightY[plane_idx]); unsigned int vp_width = chroma ? p->display_cfg->plane_descriptors[plane_idx].composition.viewport.plane1.width : p->display_cfg->plane_descriptors[plane_idx].composition.viewport.plane0.width; unsigned int vp_height = chroma ? p->display_cfg->plane_descriptors[plane_idx].composition.viewport.plane1.height : p->display_cfg->plane_descriptors[plane_idx].composition.viewport.plane0.height; unsigned int tile_width = chroma ? p->MacroTileWidthC[plane_idx] : p->MacroTileWidthY[plane_idx]; unsigned int tile_height = chroma ? p->MacroTileHeightC[plane_idx] : p->MacroTileHeightY[plane_idx]; unsigned int byte_per_pixel = chroma ? p->BytePerPixelC[plane_idx] : p->BytePerPixelY[plane_idx]; + unsigned int swath_width = chroma ? p->SwathWidthC[plane_idx] : p->SwathWidthY[plane_idx]; unsigned int copy_width; unsigned int copy_height; - unsigned int odm_combine_factor; - double odm_slice_pixels; - - if (p->ODMMode[plane_idx] == dml2_odm_mode_combine_4to1) - odm_combine_factor = 4; - else if (p->ODMMode[plane_idx] == dml2_odm_mode_combine_3to1) - odm_combine_factor = 3; - else if (p->ODMMode[plane_idx] == dml2_odm_mode_combine_2to1) - odm_combine_factor = 2; - else - odm_combine_factor = 1; - - odm_slice_pixels = (double)h_active / odm_combine_factor * h_ratio + (odm_combine_factor == 3 ? 2 : 0); /* Unaligned copy region dimensions (in pixels / lines) prior to tile alignment. - * No need to divide vp width/height by NoOfDPP. The entire viewport could be within a single ODM slice if less than the odm slice pixels + * No need to divide vp width/height by NoOfDPP. The entire viewport could be within a single pipe if less than the swath width * (e.g., multi-plane scenario with ODM combine). */ - copy_width = vertical_access ? copy_src_lines : (unsigned int)math_ceil(math_min2(odm_slice_pixels, vp_width)); - copy_height = vertical_access ? (unsigned int)math_ceil(math_min2(odm_slice_pixels, vp_height)) : copy_src_lines; + copy_width = vertical_access ? copy_src_lines : (unsigned int)math_min2((double)swath_width, (double)vp_width); + copy_height = vertical_access ? (unsigned int)math_min2((double)swath_width, (double)vp_height) : copy_src_lines; return calculate_tile_aligned_size(copy_width, copy_height, tile_width, tile_height, byte_per_pixel); } -- 2.43.0