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Ip=[165.204.84.17]; Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF00000207.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB9071 X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "amd-gfx" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Taimur Hassan This version brings along the following updates: - Fix KUnit tiled EDID size - fix hubbub read state logging - skip_lcdvdd_off for eDP link lost retrain - Don't shrink zero-area recout in full viewport visual confirm - panel specific wa not fall back to tmds - Use expanded DMUB-provided SoC BB and IP caps - Only force P-State on first plane if TTU is below WM - Program the kept-plane scaler in DC2 - Add and remove two MPO planes in DC2 - Add DC2 state facts and split the builders - Program DC2 commit stereo once - Read DCN6 SOP constraints from the idle row - Use soc_bb hostvm fraction instead of hardcoded value - Increase state if dcfclk deep sleep needed exceeds dcfclk - Flip dml2_core_utils_get_segment_horizontal_contiguous() Inputs - Update DCN6 Calcs - Add effective_number_of_dpp parameter - Read DRAM channel width from SMU init table - Update DCN42B stutter latency to match DCN42 - Expect VRAM|GTT for the DMUB framebuffer - Report QoS latency bounds and request - upsp fixes - Limit VRAM aperture retrieval to DCN6 - Make DPP_PG_CONTROL and HUBP_PG_CONTROL BLS compliant - Seed boot clocks to avoid lowering pre-OS display clocks - Account for split pipe overlap in alt channel copy size - Get OPP heads and DPP pipes by stream in dc_resource - Program ODM 2:1 and 3:1 on one stream in DC2 - Enable Replay timing sync by default Signed-off-by: Taimur Hassan Signed-off-by: Wayne Lin --- drivers/gpu/drm/amd/display/dc/dc.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 2dff1b271416..b71a9a5cd424 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -69,7 +69,7 @@ struct dcn_dsc_reg_state; struct dcn_optc_reg_state; struct dcn_dccg_reg_state; -#define DC_VER "3.2.406" +#define DC_VER "3.2.407" /** * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC -- 2.43.0