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Tsirkin" To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-devel@nongnu.org, Alex Williamson Subject: Re: [PATCH for-12.0 v2] pcie: Model DLLLA transitions on Secondary Bus Reset Message-ID: <20261112054038-mutt-send-email-mst@kernel.org> References: <20261110060205.1147027-1-clg@redhat.com> <20261111074653-mutt-send-email-mst@kernel.org> <4037a4af-1b56-4cdf-a3c2-09baf51b4641@kaod.org> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <4037a4af-1b56-4cdf-a3c2-09baf51b4641@kaod.org> Received-SPF: pass client-ip=170.10.133.124; envelope-from=mst@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 On Thu, Nov 12, 2026 at 11:28:34AM +0100, Cédric Le Goater wrote: > On 11/11/26 13:48, Michael S. Tsirkin wrote: > > On Tue, Nov 10, 2026 at 07:02:04AM +0100, Cédric Le Goater wrote: > > > Per PCIe r6.5 sec 6.6.1 and 7.5.3.8, setting the Secondary Bus Reset > > > bit on a downstream port drives the Data Link Layer to DL_Down, > > > clearing the Data Link Layer Link Active bit (DLLLA). On de-assertion > > > the link retrains and DLLLA is re-asserted. > > > > > > Currently DLLLA is only managed during plug/unplug events, so a > > > guest sees stale DLLLA=1 while SBR is in progress. > > > > > > Handle both SBR transitions in pci_bridge_write_config(), the common > > > config write path for all bridge types, guarded by > > > pci_is_express_downstream_port(). Also restore DLLLA in > > > pcie_cap_slot_reset() so that a system reset while SBR is asserted > > > does not leave DLLLA stuck at 0. > > > > > > Signed-off-by: Cédric Le Goater > > > --- > > > include/hw/pci/pcie.h | 1 + > > > hw/pci/pci_bridge.c | 13 ++++++++++++- > > > hw/pci/pcie.c | 20 ++++++++++++++++++++ > > > 3 files changed, 33 insertions(+), 1 deletion(-) > > > > > > Changes in v2 : > > > > > > - Introduced pcie_cap_update_slot_link() as suggested by Michael. > > > > > > diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h > > > index ec25e7a7de99..50fbbacb2200 100644 > > > --- a/include/hw/pci/pcie.h > > > +++ b/include/hw/pci/pcie.h > > > @@ -112,6 +112,7 @@ void pcie_cap_slot_get(PCIDevice *dev, uint16_t *slt_ctl, uint16_t *slt_sta); > > > void pcie_cap_slot_write_config(PCIDevice *dev, > > > uint16_t old_slt_ctl, uint16_t old_slt_sta, > > > uint32_t addr, uint32_t val, int len); > > > +void pcie_cap_update_slot_link(PCIDevice *dev, uint16_t bctl); > > > int pcie_cap_slot_post_load(void *opaque, int version_id); > > > void pcie_cap_slot_push_attention_button(PCIDevice *dev); > > > void pcie_cap_slot_enable_power(PCIDevice *dev); > > > diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c > > > index e85932e41a92..a11cf2f20afa 100644 > > > --- a/hw/pci/pci_bridge.c > > > +++ b/hw/pci/pci_bridge.c > > > @@ -33,6 +33,7 @@ > > > #include "qemu/units.h" > > > #include "hw/pci/pci_bridge.h" > > > #include "hw/pci/pci_bus.h" > > > +#include "hw/pci/pcie.h" > > > #include "qemu/module.h" > > > #include "qemu/range.h" > > > #include "qapi/error.h" > > > @@ -274,9 +275,19 @@ void pci_bridge_write_config(PCIDevice *d, > > > newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); > > > if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) { > > > - /* Trigger hot reset on 0->1 transition. */ > > > + /* SBR assertion (0->1): bring link down, then reset devices. */ > > > + if (pci_is_express_downstream_port(d)) { > > > + pcie_cap_update_slot_link(d, newctl); > > > + } > > > bus_cold_reset(BUS(&s->sec_bus)); > > > } > > > + > > > + if (oldctl & ~newctl & PCI_BRIDGE_CTL_BUS_RESET) { > > > + /* SBR de-assertion (1->0): bring link back up. */ > > > + if (pci_is_express_downstream_port(d)) { > > > + pcie_cap_update_slot_link(d, newctl); > > > + } > > > + } > > > } > > > void pci_bridge_disable_base_limit(PCIDevice *dev) > > > > > > I'd rather call it once, unconditionally: it's idempotent. > > > > Or if you really want: > > if ((oldctl ^ newctl) & PCI_BRIDGE_CTL_BUS_RESET) > > yes. Looks better. How's that ? > > @@ -273,6 +274,12 @@ void pci_bridge_write_config(PCIDevice * > } > newctl = pci_get_word(d->config + PCI_BRIDGE_CONTROL); > + if ((oldctl ^ newctl) & PCI_BRIDGE_CTL_BUS_RESET) { > + if (pci_is_express_downstream_port(d)) { > + pcie_cap_update_slot_link(d, newctl); > + } > + } > + > if (~oldctl & newctl & PCI_BRIDGE_CTL_BUS_RESET) { > /* Trigger hot reset on 0->1 transition. */ > bus_cold_reset(BUS(&s->sec_bus)); > > > C. LGTM > > > > > > > diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c > > > index bd00305ecca6..3b6dcd15aa44 100644 > > > --- a/hw/pci/pcie.c > > > +++ b/hw/pci/pcie.c > > > @@ -803,6 +803,8 @@ void pcie_cap_slot_reset(PCIDevice *dev) > > > PCI_EXP_SLTSTA_PDC | > > > PCI_EXP_SLTSTA_ABP); > > > + pcie_cap_update_slot_link(dev, > > > + pci_get_word(dev->config + PCI_BRIDGE_CONTROL)); > > > pcie_cap_update_power(dev); > > > hotplug_event_update_event_status(dev); > > > } > > > @@ -946,6 +948,24 @@ void pcie_cap_slot_push_attention_button(PCIDevice *dev) > > > pcie_cap_slot_event(dev, PCI_EXP_HP_EV_ABP); > > > } > > > +/* > > > + * Set DLLLA to reflect the actual link state: up iff a device is > > > + * present on the secondary bus and SBR is not asserted. > > > + */ > > > +void pcie_cap_update_slot_link(PCIDevice *dev, uint16_t bctl) > > > +{ > > > + PCIBus *sec_bus = pci_bridge_get_sec_bus(PCI_BRIDGE(dev)); > > > + uint8_t *exp_cap = dev->config + dev->exp.exp_cap; > > > + uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP); > > > + bool link_up = sec_bus->devices[0] && !(bctl & PCI_BRIDGE_CTL_BUS_RESET); > > > + > > > + if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || > > > + (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) { > > > + pci_set_word_by_mask(exp_cap + PCI_EXP_LNKSTA, > > > + PCI_EXP_LNKSTA_DLLLA, link_up); > > > + } > > > +} > > > + > > > /* root control/capabilities/status. PME isn't emulated for now */ > > > void pcie_cap_root_init(PCIDevice *dev) > > > { > > > -- > > > 2.56.0 > >