From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C4E8F606A321 for ; Thu, 12 Nov 2026 21:35:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.a=rsa-sha256 header.s=Intel header.b=R/u6Uvtf Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 8667A112371; Thu, 12 Nov 2026 21:35:28 +0000 (UTC) Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 920E6112347 for ; Thu, 12 Nov 2026 21:35:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1794519322; x=1826055322; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kfmCO702CIMLTXDVTJzs/um0J9cpDb5mzujLVWZ5234=; b=R/u6Uvtf0LXfyf+1DoqO/T2mPKfgLxA1R8+aCLkuiOI4/0SBibArl4lk 4gerftTSIknjiq26bln6Ox8+PGHOx8qrMBASYrykHRmxEAlyHtd1812o3 WMnjsfE6fj9UHQpDWCNP2hILjowQbtj3NPBmxpaGT6BBh7UUUoLcuzswn dKbf5xRa/ob+JX5rjQBUB/mLZYzLI1R2YdlCq0qy6hXOIPqS9/O/KHw3H WJkYvoS3Pb5UWuPc21SqTRAzlcc6gMwN5G4TC+LzqXc4UPwElOLoIyWf2 19Q5Ndr/c1swORikBsCZxanROomOgZNwyYQhqaOY6oh4o5NcK3Mr1lBkj w==; X-CSE-ConnectionGUID: BMlIkejARLSMpJe6ugZm5Q== X-CSE-MsgGUID: UsVllhd0Rd2aSmKzhm09BA== X-IronPort-AV: E=McAfee;i="6800,10657,11964"; a="3351727" X-IronPort-AV: E=Sophos;i="6.27,210,1787036400"; d="scan'208";a="3351727" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa112.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2026 13:35:12 -0800 X-CSE-ConnectionGUID: i/+PbIEvSdCXwcsF+n9rPg== X-CSE-MsgGUID: T74//GPPS/SArr8sEJum0w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,210,1787036400"; d="scan'208";a="8754540" Received: from dut4463arlhx.fm.intel.com ([10.105.10.189]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Nov 2026 13:35:11 -0800 From: Stuart Summers To: Cc: intel-xe@lists.freedesktop.org, rodrigo.vivi@intel.com, matthew.d.roper@intel.com, gustavo.sousa@intel.com, Stuart Summers Subject: [PATCH 7/8] drm/xe: Split out configfs data structures Date: Thu, 12 Nov 2026 21:35:12 +0000 Message-ID: <20261112213508.457213-17-stuart.summers@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261112213508.457213-10-stuart.summers@intel.com> References: <20261112213508.457213-10-stuart.summers@intel.com> X-Archived-By: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Intel-xe" X-Spam-Status: No, score=-18.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 Planning on moving debug specific configfs parameters to their own file in a future patch. In preparation for that change, move the structures in xe_configfs.c to a new _types.h file so we can easily access them in the different configfs files. Doing that separately here instead of combining with the patch that adds the debug file for ease of review. Signed-off-by: Stuart Summers Reviewed-by: Matt Roper --- drivers/gpu/drm/xe/xe_configfs.c | 43 -------------------- drivers/gpu/drm/xe/xe_configfs.h | 1 + drivers/gpu/drm/xe/xe_configfs_types.h | 55 ++++++++++++++++++++++++++ 3 files changed, 56 insertions(+), 43 deletions(-) create mode 100644 drivers/gpu/drm/xe/xe_configfs_types.h diff --git a/drivers/gpu/drm/xe/xe_configfs.c b/drivers/gpu/drm/xe/xe_configfs.c index 68d1db7bd1af..e810cd2a00be 100644 --- a/drivers/gpu/drm/xe/xe_configfs.c +++ b/drivers/gpu/drm/xe/xe_configfs.c @@ -4,7 +4,6 @@ */ #include -#include #include #include #include @@ -17,10 +16,7 @@ #include "xe_configfs.h" #include "xe_defaults.h" #include "xe_gt_types.h" -#include "xe_hw_engine_types.h" #include "xe_module.h" -#include "xe_pci_types.h" -#include "xe_sriov_types.h" /** * DOC: Xe Configfs @@ -290,45 +286,6 @@ * # rmdir /sys/kernel/config/xe/0000:03:00.0/ */ -/* Similar to struct xe_bb, but not tied to HW (yet) */ -struct wa_bb { - u32 *cs; - u32 len; /* in dwords */ -}; - -struct xe_config_group_device { - struct config_group group; - struct config_group sriov; - - /* - * Fields sorted by type (largest first) then name: struct arrays, - * u64, u32/unsigned int, u8, bool, sub-structs last. Within each - * type, entries are sorted alphabetically. - */ - struct xe_config_device { - struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX]; - struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX]; - u64 engines_allowed; - u64 gt_types_allowed; - u32 migrate_ulls_period_ms; - u8 survivability_mode; - bool enable_multi_queue; - bool enable_psmi; - bool enable_vram_page_offline; - struct { - unsigned int max_vfs; - bool admin_only_pf; - } sriov; - } config; - - /* protects attributes */ - struct mutex lock; - /* matching descriptor */ - const struct xe_device_desc *desc; - /* tentative SR-IOV mode */ - enum xe_sriov_mode mode; -}; - static const struct xe_config_device device_defaults = { .engines_allowed = U64_MAX, .gt_types_allowed = U64_MAX, diff --git a/drivers/gpu/drm/xe/xe_configfs.h b/drivers/gpu/drm/xe/xe_configfs.h index 78aa320e60df..97ee615e3eb6 100644 --- a/drivers/gpu/drm/xe/xe_configfs.h +++ b/drivers/gpu/drm/xe/xe_configfs.h @@ -9,6 +9,7 @@ #include #include +#include "xe_configfs_types.h" #include "xe_defaults.h" #include "xe_hw_engine_types.h" #include "xe_module.h" diff --git a/drivers/gpu/drm/xe/xe_configfs_types.h b/drivers/gpu/drm/xe/xe_configfs_types.h new file mode 100644 index 000000000000..b1e351761d69 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_configfs_types.h @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2026 Intel Corporation + */ +#ifndef _XE_CONFIGFS_TYPES_H_ +#define _XE_CONFIGFS_TYPES_H_ + +#include +#include +#include + +#include "xe_hw_engine_types.h" +#include "xe_pci_types.h" +#include "xe_sriov_types.h" + +/* Similar to struct xe_bb, but not tied to HW (yet) */ +struct wa_bb { + u32 *cs; + u32 len; /* in dwords */ +}; + +struct xe_config_group_device { + struct config_group group; + struct config_group sriov; + + /* + * Fields sorted by type (largest first) then name: struct arrays, + * u64, u32/unsigned int, u8, bool, sub-structs last. Within each + * type, entries are sorted alphabetically. + */ + struct xe_config_device { + struct wa_bb ctx_restore_mid_bb[XE_ENGINE_CLASS_MAX]; + struct wa_bb ctx_restore_post_bb[XE_ENGINE_CLASS_MAX]; + u64 engines_allowed; + u64 gt_types_allowed; + u32 migrate_ulls_period_ms; + u8 survivability_mode; + bool enable_multi_queue; + bool enable_psmi; + bool enable_vram_page_offline; + struct { + unsigned int max_vfs; + bool admin_only_pf; + } sriov; + } config; + + /* protects attributes */ + struct mutex lock; + /* matching descriptor */ + const struct xe_device_desc *desc; + /* tentative SR-IOV mode */ + enum xe_sriov_mode mode; +}; + +#endif /* _XE_CONFIGFS_TYPES_H_ */ -- 2.43.0