From: Conor Dooley <conor@kernel.org>
To: Svyatoslav Ryhel <clamor95@gmail.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Thierry Reding <thierry.reding@kernel.org>,
Jonathan Hunter <jonathanh@nvidia.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Mikko Perttunen <mperttunen@nvidia.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v1 1/2] dt-bindings: clock: tegra114: Add IDs for CSI pad clocks
Date: Fri, 13 Nov 2026 16:49:51 +0000 [thread overview]
Message-ID: <20261113-brunch-rectify-96bdf183eb78@spud> (raw)
In-Reply-To: <20261113145708.261530-2-clamor95@gmail.com>
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On Fri, Nov 13, 2026 at 04:57:07PM +0200, Svyatoslav Ryhel wrote:
> Tegra114 has CSI pad clock enable bits embedded into PLLD/PLLD2 registers.
> Add ids for these clocks. Additionally, move TEGRA114_CLK_CLK_MAX into
> clk-tegra114 source.
>
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
> drivers/clk/tegra/clk-tegra114.c | 1 +
> include/dt-bindings/clock/tegra114-car.h | 3 ++-
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
> index 97f5500b13b5f..80b7f64125d92 100644
> --- a/drivers/clk/tegra/clk-tegra114.c
> +++ b/drivers/clk/tegra/clk-tegra114.c
> @@ -47,6 +47,7 @@
> #define CPU_FINETRIM_R_FCPU_6_MASK (0x3 << CPU_FINETRIM_R_FCPU_6_SHIFT)
>
> #define TEGRA114_CLK_PERIPH_BANKS 5
> +#define TEGRA114_CLK_CLK_MAX 314
>
> #define PLLC_BASE 0x80
> #define PLLC_MISC2 0x88
> diff --git a/include/dt-bindings/clock/tegra114-car.h b/include/dt-bindings/clock/tegra114-car.h
> index a93426f008acc..b53f5942f4bae 100644
> --- a/include/dt-bindings/clock/tegra114-car.h
> +++ b/include/dt-bindings/clock/tegra114-car.h
> @@ -341,6 +341,7 @@
> #define TEGRA114_CLK_DSIA_MUX 309
> #define TEGRA114_CLK_DSIB_MUX 310
> #define TEGRA114_CLK_XUSB_SS_DIV2 311
> -#define TEGRA114_CLK_CLK_MAX 312
Good riddance.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
> +#define TEGRA114_CLK_CSIA_PAD 312
> +#define TEGRA114_CLK_CSIB_PAD 313
>
> #endif /* _DT_BINDINGS_CLOCK_TEGRA114_CAR_H */
> --
> 2.53.0
>
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next prev parent reply other threads:[~2026-11-13 16:49 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 14:57 [PATCH v1 0/2] clk: tegra114: Add CSI pad clock gates Svyatoslav Ryhel
2026-11-13 14:57 ` [PATCH v1 1/2] dt-bindings: clock: tegra114: Add IDs for CSI pad clocks Svyatoslav Ryhel
2026-11-13 16:49 ` Conor Dooley [this message]
2026-11-13 14:57 ` [PATCH v1 2/2] clk: tegra114: Add CSI pad clock gates Svyatoslav Ryhel
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