From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794585876; b=D7ySwz/IzbxyYWrpmOSMrdvuY2GXm6c16NLaZMpON28QqtH3qJkWJL1vqJI8EqlOK7YC Ps6JEwdcc9MeC7kO5AiNF91ZcW6wIa002MAh4eCwP6D6Ym23YPVxOXQmkh9qMakL3V4x0 yEN8FY56nP6+G5UbSQjGajos4EjFCzNgZJghFNYDhgVAQeroGC1t+yNMc/bPQiEhboYu9 jN5xAxHXXd91nAjWeZFM3m7HzRAv+JRABbEZddR7xK4Kn80qwOE4Y7DdVje7UwGt85Jpx UWVbhFg+bta5nzXcJVacywM4Xw2WnDOWYp7srHWlUbgBjnMpvBIoznYCekqReVE+o4g== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794585876; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:User-Agent:X-stable:X-Patchwork-Hint: MIME-Version:Content-Transfer-Encoding; bh=/aN0eyUQfBDfon/QKQP/qKooRmSi0gLDcZtGGzJQ640=; b=MKW5xKLbHXv2xGws9AFkPWb/sKDMPQP7qLjmOeWHbgD9d+MScjs9WOApeoSZOwwaRQKl JZIDkZAem3nlK/6jFd5kSVP8Y3nS1dxuh/Zya+HWDyG7qkk31+wBqu1zjJ7dHXfAVa4mL PY0bIveLX7Gw7rkY5uJQvBG2mrGeh6X2iqY2E07TTqoHmUZZ1Wrx9ptXLWzKWzPS4FMDP kNiht6QlGN8RuugU+68NmouA5lN66+JQmz73VY+cmH9gTKicJ55RKqJ1oFDKo5H/6bav+ JHt90ALQFaZt3HC+tSsgMa9+p2aGLosm1t4GlGiQTJLOcIPw6rlORPS3bunf3C0x9jQ== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b="Ambx/vLO"; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2EA12606EA86; Fri, 13 Nov 2026 16:04:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=Ambx/vLO Received: by smtp.kernel.org (Postfix) with ESMTPSA id CEB631F000C6; Fri, 13 Nov 2026 16:04:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1794585876; bh=/aN0eyUQfBDfon/QKQP/qKooRmSi0gLDcZtGGzJQ640=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=Ambx/vLOoqogCH7vXi/9EgvowuNVkgl3IK6u5tFIPI0dh5ZCUoBgZJUPBWy5nnv8F iUXN2wy2f3tHwwT/6Ekkzg51x7rVaefZKE7y+gr7G3JygjRoKtxY/MsVbpOwIG9qyb kUEuncaQfzuPuuwc75e+zrSTxf7PmjjWsefPfvJA= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Eugen Hristev , Balakrishnan Sambath , Hans Verkuil , Sasha Levin Subject: [PATCH 7.3 445/507] media: microchip-isc: fix WB offset and gain register field masking Date: Fri, 13 Nov 2026 10:52:29 -0500 Message-ID: <20261113153811.823141531@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261113153753.358973689@linuxfoundation.org> References: <20261113153753.358973689@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore X-Mailing-List: patches@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 7.3-stable review patch. If anyone has any objections, please let me know. ------------------ From: Balakrishnan Sambath [ Upstream commit 6e9eaa3b93870e4edac1bd2539fe113c24663eaf ] ISC_WB_O_* and ISC_WB_G_* each pack two 13-bit fields. A negative offset sign-extends and corrupts the adjacent field. Add masks for the two fields and write them with FIELD_PREP(), which masks each value into its field, so sign extension can no longer bleed across. Fixes: 73c1a577b839 ("media: atmel: atmel-isc: reworked white balance feature") Cc: stable@vger.kernel.org Reviewed-by: Eugen Hristev Signed-off-by: Balakrishnan Sambath Signed-off-by: Hans Verkuil Signed-off-by: Sasha Levin --- .../platform/microchip/microchip-isc-base.c | 16 ++++++++-------- .../platform/microchip/microchip-isc-regs.h | 6 ++++++ 2 files changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/media/platform/microchip/microchip-isc-base.c b/drivers/media/platform/microchip/microchip-isc-base.c index e5ecf6ffd24a8..963d5fd53b589 100644 --- a/drivers/media/platform/microchip/microchip-isc-base.c +++ b/drivers/media/platform/microchip/microchip-isc-base.c @@ -63,17 +63,17 @@ static inline void isc_update_awb_ctrls(struct isc_device *isc) /* In here we set our actual hw pipeline config */ regmap_write(isc->regmap, ISC_WB_O_RGR, - ((ctrls->offset[ISC_HIS_CFG_MODE_R])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GR]) << 16)); + FIELD_PREP(ISC_WB_O_LO, ctrls->offset[ISC_HIS_CFG_MODE_R]) | + FIELD_PREP(ISC_WB_O_HI, ctrls->offset[ISC_HIS_CFG_MODE_GR])); regmap_write(isc->regmap, ISC_WB_O_BGB, - ((ctrls->offset[ISC_HIS_CFG_MODE_B])) | - ((ctrls->offset[ISC_HIS_CFG_MODE_GB]) << 16)); + FIELD_PREP(ISC_WB_O_LO, ctrls->offset[ISC_HIS_CFG_MODE_B]) | + FIELD_PREP(ISC_WB_O_HI, ctrls->offset[ISC_HIS_CFG_MODE_GB])); regmap_write(isc->regmap, ISC_WB_G_RGR, - ctrls->gain[ISC_HIS_CFG_MODE_R] | - (ctrls->gain[ISC_HIS_CFG_MODE_GR] << 16)); + FIELD_PREP(ISC_WB_G_LO, ctrls->gain[ISC_HIS_CFG_MODE_R]) | + FIELD_PREP(ISC_WB_G_HI, ctrls->gain[ISC_HIS_CFG_MODE_GR])); regmap_write(isc->regmap, ISC_WB_G_BGB, - ctrls->gain[ISC_HIS_CFG_MODE_B] | - (ctrls->gain[ISC_HIS_CFG_MODE_GB] << 16)); + FIELD_PREP(ISC_WB_G_LO, ctrls->gain[ISC_HIS_CFG_MODE_B]) | + FIELD_PREP(ISC_WB_G_HI, ctrls->gain[ISC_HIS_CFG_MODE_GB])); } static inline void isc_reset_awb_ctrls(struct isc_device *isc) diff --git a/drivers/media/platform/microchip/microchip-isc-regs.h b/drivers/media/platform/microchip/microchip-isc-regs.h index 185ef0eab7ad3..cabecf128b37a 100644 --- a/drivers/media/platform/microchip/microchip-isc-regs.h +++ b/drivers/media/platform/microchip/microchip-isc-regs.h @@ -149,6 +149,12 @@ /* ISC White Balance Gain for B, GB Register */ #define ISC_WB_G_BGB 0x0000006c +/* Each WB offset/gain register packs two 13-bit fields, low and high */ +#define ISC_WB_O_LO GENMASK(12, 0) /* R or B offset [12:0] */ +#define ISC_WB_O_HI GENMASK(28, 16) /* GR or GB offset [28:16] */ +#define ISC_WB_G_LO GENMASK(12, 0) /* R or B gain [12:0] */ +#define ISC_WB_G_HI GENMASK(28, 16) /* GR or GB gain [28:16] */ + /* ISC Color Filter Array Control Register */ #define ISC_CFA_CTRL 0x00000070 -- 2.53.0