From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794591253; b=Jn3Zszuoq1MwSc+S+t1iHCwnzVZb/Sdz14dOBtnfeECAmlqpMdsz9l0L8nW95siIy9qS fep3YM3M5yujDs3O81/rWWaCQCuOhN3EQ2e5CPT1WoRhB+OilqHYTUd0MRvndlDNuwij/ J3vtjQFte2VT1HicFK6U28RYnIGhD4sPgIKHtQtuFOWFiE8+iuEcRkdCaZSyTyN3qjYrJ 2VmHRlYQVR2Ywh49xPXWStU20vSuTzoIZ/7lsVdOfEE40KKHSd5oyYLfS/Iq4wTIm15EL WNsrFN3hiPlKnJZrAiOIrifwiPMbnsMkudyFrn6P83JAELE0F/Lq/iN8drXgRnY39Fg== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794591253; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:User-Agent:X-stable:X-Patchwork-Hint: MIME-Version:Content-Transfer-Encoding; bh=jTbnHswRK7V7RKhZ9avPzEI58FwP3+/rVEd31wvZzWw=; b=e+mWrBiNjcM+bQhy704lKzJRpm+Fovn/WF0dR3hOXH+7AJFYbqmyJef9a1HHTSItXu/R lG2/BqqxdQyWiuSnXi39Ro3GsfAdnh8uN2BBDU9xOepAEFDgKN5CqIimLz+wLPK34k4cT tPqDKWDXg/h5DXuhrd4p0GUS7Y4Ew+gdK/YafrJauyKgKsZ49I+wKMrigCZSddfEp5ko4 5lL328P3biMqnMmtmqrWZJWNRRbMwVI21Mn7jbmNTT+LJz8/R78nOI9URoqRjPpiYcHkp CwAE9lnHtqjgmlk2jNT6/zBZDLgMHLgSl2O6DFyOMGNNJvezWJ9ni2Kxqpnb2cHVlaA== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=b6Bmsy77; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2A85E6076F81; Fri, 13 Nov 2026 17:34:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=b6Bmsy77 Received: by smtp.kernel.org (Postfix) with ESMTPSA id CB8531F000C4; Fri, 13 Nov 2026 17:34:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1794591253; bh=jTbnHswRK7V7RKhZ9avPzEI58FwP3+/rVEd31wvZzWw=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=b6Bmsy77OjRVWH6ayivUrOClnmvIyqHIiTiAqZUjxH+veKBfF0lhQ5hz41kHz8RO9 E0YfdPXy66MfaiQKCj8I0xRxwzhXnumIQHwCVfbDoSxvOa0WEEavjNxH+8FnqAsHvA LbfIgFbMxZIrYao1u2OhA8Ooa2fY6WHb9nb72QP8= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Lucas Stach , Christian Gmeiner , Sasha Levin Subject: [PATCH 6.12 376/670] drm/etnaviv: Flush the tile status cache through both the PE and BLT Date: Fri, 13 Nov 2026 10:49:00 -0500 Message-ID: <20261113153824.526468741@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261113153811.177190860@linuxfoundation.org> References: <20261113153811.177190860@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore X-Mailing-List: patches@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Christian Gmeiner [ Upstream commit c1a757f8df1363032623fa9b1baaba0dcf34de6d ] Since commit f232d9ec029c ("drm/etnaviv: fix TS cache flushing on GPUs with BLT engine"), jobs on GPUs with a BLT engine use a BLT command to flush the tile status cache instead of TS_FLUSH_CACHE, which is broken on most of these GPUs. GC7000 r6008/r6009 and GC8200 r6401 are the other way around: TS_FLUSH_CACHE works, but the BLT command does not flush the cache. The vendor driver handles these GPUs using TS_FLUSH_CACHE, but the etnaviv kernel driver has no way to identify them. As a result, dirty tile status cache lines survive the end of a job. They are written back by the next cache flush, using the page table of the job issuing it. If that job belongs to another process, the write goes to the wrong address space. On GC7000 r6009 this causes MMU faults and GPU recoveries blamed on an innocent process. I see around 1100 per run of a multisample depth/stencil test running alongside two other GPU clients. Emit both flushes at the end of every job on GPUs with a BLT engine. Whichever does not work on a given GPU is a no-op. Since dirty lines are only written back once, this costs one additional state load per job. Fixes: f232d9ec029c ("drm/etnaviv: fix TS cache flushing on GPUs with BLT engine") Cc: stable@vger.kernel.org Reviewed-by: Lucas Stach Link: https://patch.msgid.link/20261102-etna-pe-ts-flush-v1-1-e4454ed86f85@igalia.com Signed-off-by: Christian Gmeiner Signed-off-by: Sasha Levin --- drivers/gpu/drm/etnaviv/etnaviv_buffer.c | 40 +++++++++++------------- 1 file changed, 18 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c index 88385dc3b30d8..4f22e373ed346 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_buffer.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_buffer.c @@ -230,6 +230,17 @@ u16 etnaviv_buffer_config_pta(struct etnaviv_gpu *gpu, unsigned short id) return buffer->user_size / 8; } +static void etnaviv_cmd_flush_ts(struct etnaviv_cmdbuf *buffer, bool has_blt) +{ + CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE, VIVS_TS_FLUSH_CACHE_FLUSH); + + if (has_blt) { + CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1); + CMD_LOAD_STATE(buffer, VIVS_BLT_SET_COMMAND, 0x1); + CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0); + } +} + void etnaviv_buffer_end(struct etnaviv_gpu *gpu) { struct etnaviv_cmdbuf *buffer = &gpu->buffer; @@ -253,7 +264,7 @@ void etnaviv_buffer_end(struct etnaviv_gpu *gpu) unsigned int dwords = 7; if (has_blt) - dwords += 10; + dwords += 11; link_target = etnaviv_buffer_reserve(gpu, buffer, dwords); @@ -266,16 +277,8 @@ void etnaviv_buffer_end(struct etnaviv_gpu *gpu) CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0); } CMD_LOAD_STATE(buffer, VIVS_GL_FLUSH_CACHE, flush); - if (gpu->exec_state == ETNA_PIPE_3D) { - if (has_blt) { - CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1); - CMD_LOAD_STATE(buffer, VIVS_BLT_SET_COMMAND, 0x1); - CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0); - } else { - CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE, - VIVS_TS_FLUSH_CACHE_FLUSH); - } - } + if (gpu->exec_state == ETNA_PIPE_3D) + etnaviv_cmd_flush_ts(buffer, has_blt); CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); if (has_blt) { @@ -462,12 +465,12 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state, return_dwords = 7; /* - * When the BLT engine is present we need 6 more dwords in the return + * When the BLT engine is present we need 7 more dwords in the return * target: 3 enable/flush/disable + 4 enable/semaphore stall/disable, - * but we don't need the normal TS flush state. + * on top of the normal TS flush state. */ if (has_blt) - return_dwords += 6; + return_dwords += 7; return_target = etnaviv_buffer_reserve(gpu, buffer, return_dwords); CMD_LINK(cmdbuf, return_dwords, return_target); @@ -484,14 +487,7 @@ void etnaviv_buffer_queue(struct etnaviv_gpu *gpu, u32 exec_state, VIVS_GL_FLUSH_CACHE_DEPTH | VIVS_GL_FLUSH_CACHE_COLOR | VIVS_GL_FLUSH_CACHE_SHADER_L1); - if (has_blt) { - CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x1); - CMD_LOAD_STATE(buffer, VIVS_BLT_SET_COMMAND, 0x1); - CMD_LOAD_STATE(buffer, VIVS_BLT_ENABLE, 0x0); - } else { - CMD_LOAD_STATE(buffer, VIVS_TS_FLUSH_CACHE, - VIVS_TS_FLUSH_CACHE_FLUSH); - } + etnaviv_cmd_flush_ts(buffer, has_blt); } CMD_SEM(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); CMD_STALL(buffer, SYNC_RECIPIENT_FE, SYNC_RECIPIENT_PE); -- 2.53.0