From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=100.103.45.18 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1794591473; b=LcFAsVts0fDVVGrPawNLU75k0nqnVCPP+wYAambwgULTxgF/PzVPQ9kRCvcAx9Wi5S1L 8aj/48heABEp+wcYFsGQ7Y397hpUP4Nj7FPNFRcpqVRo3k8hnCJhYt0R9E3ERORMCDubS 5qEO8pN11y+fYrEHcY/tHBR+SafMumk8nPOaw7bP1tPfHnAmZ4kCDfz+2lcLKazsG0Zc9 1WKyNUNvpkaL//59OIMceJieP+YIyCAopyjp0vh2BxW3yFwpccyPYfcbNZIuppi6xcb/h dYUL0JE+QTonIob1BVFKibP2TQXuzFPDZ8ZFWAcK6LC3waIhnwMLpYGBY/Kvl6fnKng== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1794591473; h=Received:DKIM-Signature:From:To:Cc:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:User-Agent:X-stable:X-Patchwork-Hint: MIME-Version:Content-Transfer-Encoding; bh=jbgtnClixA9kcfyjo1t19URLChwiPCiUQXlMYCTHa00=; b=a3y2YUqDr5kk29xCmz3LHVqiquEdh5qrUVkZRTMAN42+Zi4LgmpUEqpPmvabM/qk6QJL m4/ljcqLCOjD41v3pS+qv1mzkyR2OymIqLKk2P9Rf7PHgaXAItmY+PXxX9s1y4//IWvFO WJseBIcKLb2CEGuI3s5Px47UsrxVzXEm2JD6BCJFL048Z9gLaQfzTo11cNSA8sXXjk7mm PEhgleBTEx1MdDGLemjEGvenr/UYGO1KV30/0RvLWcdgVlJS8nQRRHvKI4GpKG+cgYAIe XlJMHsohGubpEnBAO18wgjRr7LRx2RRHwX+iWEtySqxdgSt3Nwm0H+FEgV/5P+LVH3g== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=WLFiY2EF; arc=none smtp.remote-ip=100.103.45.18 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6F61C607D2D5; Fri, 13 Nov 2026 17:37:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linuxfoundation.org header.i=@linuxfoundation.org header.a=rsa-sha256 header.s=korg header.b=WLFiY2EF Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0749B1F000C5; Fri, 13 Nov 2026 17:37:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linuxfoundation.org; s=korg; t=1794591473; bh=jbgtnClixA9kcfyjo1t19URLChwiPCiUQXlMYCTHa00=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=WLFiY2EFGlViK8xt+T9MFox/QdLQctjtE2hd0PsAdWEYGdq4PSUhquzVZhAc1navZ 41pcZvl5GDMANei0wkHVzroiXptIXkOx4ge2Bh1sKzi73+LVx5C8zvxxuNiqKSzggS on7LkTagLreljqsqOR/6naHUQlodBsDuk8cJJI/4= From: Greg Kroah-Hartman To: stable@vger.kernel.org Cc: Greg Kroah-Hartman , patches@lists.linux.dev, Dragan Simic , Shawn Lin , Geraldo Nascimento , Manivannan Sadhasivam , Bjorn Helgaas , Sasha Levin Subject: [PATCH 6.12 555/670] PCI: rockchip: Drive at 2.5 GT/s, error other speeds Date: Fri, 13 Nov 2026 10:51:59 -0500 Message-ID: <20261113153830.692680267@linuxfoundation.org> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261113153811.177190860@linuxfoundation.org> References: <20261113153811.177190860@linuxfoundation.org> User-Agent: quilt/0.69 X-stable: review X-Patchwork-Hint: ignore X-Mailing-List: stable@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit 6.12-stable review patch. If anyone has any objections, please let me know. ------------------ From: Geraldo Nascimento [ Upstream commit 84d08ff902f1ec01177fef1a21a38934927f5aee ] Configure the core to be driven at 2.5 GT/s Link Speed and ignore any other speed with a warning. Also drop the 5.0 GT/s Link Speed defines from Rockchip PCIe header. The reason is that Shawn Lin from Rockchip has reiterated that there may be danger of "catastrophic failure" in using their PCIe with 5.0 GT/s speeds. While Rockchip has done so informally without issuing a proper errata, and the particulars are thus unknown, this may cause data loss or worse. This change is corroborated by RK3399 official datasheet [1], which states maximum link speed for this platform is 2.5 GT/s. [1] https://opensource.rock-chips.com/images/d/d7/Rockchip_RK3399_Datasheet_V2.1-20200323.pdf Fixes: 956cd99b35a8 ("PCI: rockchip: Separate common code from RC driver") Reported-by: Dragan Simic Reported-by: Shawn Lin Link: https://lore.kernel.org/all/ffd05070-9879-4468-94e3-b88968b4c21b@rock-chips.com/ Signed-off-by: Geraldo Nascimento Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Helgaas Reviewed-by: Dragan Simic Reviewed-by: Shawn Lin Cc: stable@vger.kernel.org Link: https://patch.msgid.link/7421df7a7b7778ee99363cccfdfabbfa8aa6ab5e.1781622998.git.geraldogabriel@gmail.com [ sashal: Adjusted context to preserve existing HIWORD_UPDATE macros instead of upstream HWORD macros. ] Signed-off-by: Sasha Levin --- drivers/pci/controller/pcie-rockchip.c | 14 ++++++-------- drivers/pci/controller/pcie-rockchip.h | 3 --- 2 files changed, 6 insertions(+), 11 deletions(-) diff --git a/drivers/pci/controller/pcie-rockchip.c b/drivers/pci/controller/pcie-rockchip.c index c07d7129f1c7c..6a970dc766d4d 100644 --- a/drivers/pci/controller/pcie-rockchip.c +++ b/drivers/pci/controller/pcie-rockchip.c @@ -66,8 +66,10 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip) } rockchip->link_gen = of_pci_get_max_link_speed(node); - if (rockchip->link_gen < 0 || rockchip->link_gen > 2) - rockchip->link_gen = 2; + if (rockchip->link_gen < 0 || rockchip->link_gen >= 2) { + rockchip->link_gen = 1; + dev_warn(dev, "invalid max-link-speed, limited to 2.5 GT/s\n"); + } rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core"); if (IS_ERR(rockchip->core_rst)) { @@ -237,12 +239,8 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip) goto err_exit_phy; } - if (rockchip->link_gen == 2) - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, - PCIE_CLIENT_CONFIG); - else - rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, - PCIE_CLIENT_CONFIG); + rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, + PCIE_CLIENT_CONFIG); regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE | PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes); diff --git a/drivers/pci/controller/pcie-rockchip.h b/drivers/pci/controller/pcie-rockchip.h index d916fcc8badb8..5629ac4a7439b 100644 --- a/drivers/pci/controller/pcie-rockchip.h +++ b/drivers/pci/controller/pcie-rockchip.h @@ -37,7 +37,6 @@ #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040) #define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0) #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0) -#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080) #define PCIE_CLIENT_LEGACY_INT_CTRL (PCIE_CLIENT_BASE + 0x0c) #define PCIE_CLIENT_INT_IN_ASSERT HIWORD_UPDATE_BIT(0x0002) #define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0) @@ -183,8 +182,6 @@ (((x) & PCIE_CLIENT_DEBUG_LTSSM_MASK) == PCIE_CLIENT_DEBUG_LTSSM_L2) #define PCIE_LINK_UP(x) \ (((x) & PCIE_CLIENT_LINK_STATUS_MASK) == PCIE_CLIENT_LINK_STATUS_UP) -#define PCIE_LINK_IS_GEN2(x) \ - (((x) & PCIE_CORE_PL_CONF_SPEED_MASK) == PCIE_CORE_PL_CONF_SPEED_5G) #define RC_REGION_0_ADDR_TRANS_H 0x00000000 #define RC_REGION_0_ADDR_TRANS_L 0x00000000 -- 2.53.0