From: Florian Fainelli <f.fainelli@gmail.com>
To: linux-mips@vger.kernel.org
Cc: Florian Fainelli <f.fainelli@gmail.com>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Jonathan Corbet <corbet@lwn.net>,
Shuah Khan <skhan@linuxfoundation.org>,
Randy Dunlap <rdunlap@infradead.org>,
Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Jiri Olsa <jolsa@kernel.org>, Ian Rogers <irogers@google.com>,
Adrian Hunter <adrian.hunter@intel.com>,
James Clark <james.clark@linaro.org>,
Thomas Gleixner <tglx@kernel.org>,
linux-doc@vger.kernel.org (open list:DOCUMENTATION),
linux-kernel@vger.kernel.org (open list),
linux-perf-users@vger.kernel.org (open list:PERFORMANCE EVENTS
SUBSYSTEM), "Maciej W. Rozycki" <macro@orcam.me.uk>
Subject: [PATCH v2 1/3] MIPS: SiByte: Wire up the CPU interrupt controller
Date: Fri, 13 Nov 2026 15:33:54 -0800 [thread overview]
Message-ID: <20261113233358.538698-2-f.fainelli@gmail.com> (raw)
In-Reply-To: <20261113233358.538698-1-f.fainelli@gmail.com>
Initialize the MIPS CPU interrupt controller on SB1250 and BCM1480 so
CPU-local interrupts have a configured irq_chip and handler. Reserve IRQs
128 through 135 above both interrupt mapper ranges, and dispatch BCM1480
IP7 through the CPU controller as SB1250 already does.
This provides the CPU-local IP7 interrupt needed by the SB1 performance
counters without overlapping the SiByte interrupt mapper IRQ numbers.
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/mips/include/asm/mach-sibyte/irq.h | 10 ++++++++++
arch/mips/sibyte/bcm1480/irq.c | 7 ++++++-
arch/mips/sibyte/sb1250/irq.c | 3 +++
3 files changed, 19 insertions(+), 1 deletion(-)
create mode 100644 arch/mips/include/asm/mach-sibyte/irq.h
diff --git a/arch/mips/include/asm/mach-sibyte/irq.h b/arch/mips/include/asm/mach-sibyte/irq.h
new file mode 100644
index 000000000000..b7073830d2ec
--- /dev/null
+++ b/arch/mips/include/asm/mach-sibyte/irq.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __ASM_MACH_SIBYTE_IRQ_H
+#define __ASM_MACH_SIBYTE_IRQ_H
+
+/* Keep CPU-local interrupts above both SiByte interrupt mapper ranges. */
+#define MIPS_CPU_IRQ_BASE 128
+
+#include <asm/mach-generic/irq.h>
+
+#endif
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 4c18a2c755d2..5eff85a8659b 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -15,6 +15,7 @@
#include <asm/irq_regs.h>
#include <asm/signal.h>
#include <asm/io.h>
+#include <asm/irq_cpu.h>
#include <asm/sibyte/bcm1480_regs.h>
#include <asm/sibyte/bcm1480_int.h>
@@ -242,6 +243,8 @@ void __init arch_init_irq(void)
unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
STATUSF_IP1 | STATUSF_IP0;
+ mips_cpu_irq_init();
+
/* Default everything to IP2 */
/* Start with _high registers which has no bit 0 interrupt source */
for (i = 1; i < BCM1480_NR_IRQS_HALF; i++) { /* was I0 */
@@ -337,7 +340,9 @@ asmlinkage void plat_irq_dispatch(void)
pending = read_c0_cause() & read_c0_status();
- if (pending & CAUSEF_IP4)
+ if (pending & CAUSEF_IP7)
+ do_IRQ(MIPS_CPU_IRQ_BASE + 7);
+ else if (pending & CAUSEF_IP4)
do_IRQ(K_BCM1480_INT_TIMER_0 + cpu);
#ifdef CONFIG_SMP
else if (pending & CAUSEF_IP3)
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index 57943fe3ac03..2df115269f81 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -15,6 +15,7 @@
#include <asm/signal.h>
#include <asm/time.h>
#include <asm/io.h>
+#include <asm/irq_cpu.h>
#include <asm/sibyte/sb1250_regs.h>
#include <asm/sibyte/sb1250_int.h>
@@ -225,6 +226,8 @@ void __init arch_init_irq(void)
unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
STATUSF_IP1 | STATUSF_IP0;
+ mips_cpu_irq_init();
+
/* Default everything to IP2 */
for (i = 0; i < SB1250_NR_IRQS; i++) { /* was I0 */
__raw_writeq(IMR_IP2_VAL,
--
2.53.0
next prev parent reply other threads:[~2026-11-13 23:34 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 23:33 [PATCH v2 0/3] MIPS: SiByte: Add HW PMU support Florian Fainelli
2026-11-13 23:33 ` Florian Fainelli [this message]
2026-11-13 23:33 ` [PATCH v2 2/3] MIPS: perf: Add SB1 userspace callchain unwinding Florian Fainelli
2026-11-13 23:33 ` [PATCH v2 3/3] MIPS: perf: Add SB1 and SB1A performance counter support Florian Fainelli
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