Re: [PATCH] mm/hmm: reject shadow-stack mappings

[Jason Gunthorpe <jgg@nvidia.com>]

On Fri, Nov 13, 2026 at 03:41:33PM -0500, Gregory Price (Meta) wrote:
> On 2026-11-13 16:03 -0400, Jason Gunthorpe wrote:
> > On Fri, Nov 13, 2026 at 02:55:36PM -0500, Gregory Price (Meta) wrote:
> > > HMM can grant ordinary device write access to a userspace shadow stack.
> > > On x86, pte_write() is true for a shadow-stack PTE, so a populated page
> > > can be returned with HMM_PFN_WRITE without taking a CPU write fault.
> > 
> > I'm not sure I understand this? The pte is writable but you don't want
> > only DMA to write to it?
> >
> > Is there something special on x86 that makes the shadow stack pte
> > non-writable by the CPU?
> >
> 
> Some of the context is here:
> https://lore.kernel.org/all/20261111-mason-migrate-et-al-fixes-v1-10-3d2454362e8d@kernel.org/
> 
> We had a similar issue with migration, but this should handle the DMA
> case as well.
> 
> It's "technically writable" but the kernel is supposed to prevent that.

Bah, it's not writable at all. The CPU PTE has write disabled and
someone thought it was a good idea to make pte_write() return true
because the CPU allows writes through a special instruction on this
special PTE? So now all the places like this think its writable, when
it really isn't.

You could also fix this by having something like pte_real_write() or
whatever that doesn't lie about the write bit in the PTE :|

The patch is still fine, in that it matches what everything else does,
but I'd include these details someplace..

Jason