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Peter Anvin" , Alex Deucher , =?UTF-8?q?Christian=20K=C3=B6nig?= , David Airlie , Simona Vetter , Harry Wentland , Leo Li , Rodrigo Siqueira , Kenneth Feng , Hans de Goede , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , linux-pci@vger.kernel.org (open list:PCI SUBSYSTEM), linux-kernel@vger.kernel.org (open list:X86 ARCHITECTURE (32-BIT AND 64-BIT)), amd-gfx@lists.freedesktop.org (open list:RADEON and AMDGPU DRM DRIVERS), dri-devel@lists.freedesktop.org (open list:DRM DRIVERS), platform-driver-x86@vger.kernel.org (open list:X86 PLATFORM DRIVERS) Subject: [PATCH v2 09/12] drm/amdgpu: Catch register access while GMUX keeps the GPU off Date: Sat, 14 Nov 2026 11:06:33 -0500 Message-ID: <20261114160731.3756-10-atharvatiwarilinuxdev@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261114160731.3756-1-atharvatiwarilinuxdev@gmail.com> References: <20261114160731.3756-1-atharvatiwarilinuxdev@gmail.com> X-Archived-By: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "dri-devel" X-Spam-Status: No, score=-15.8 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=4.0.1 X-Spam-Checker-Version: SpamAssassin 4.0.1 (2024-03-26) on aws-us-west-2-korg-listserv-alma10-1 From: Andre Eikmeyer As mentioned previous any access to the GPU when the GMUX has shut off the rails results in a CPU CATTER, skip and report any register access after the GPU was runtime suspended for GMUX power-off. Tested-by: Sebastian Zygadlo Tested-by: Yossef Osman Signed-off-by: Andre Eikmeyer Signed-off-by: Atharva Tiwari --- drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 + drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 5 ++++ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | 5 ++++ .../gpu/drm/amd/amdgpu/amdgpu_reg_access.c | 24 +++++++++++++++++++ 4 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h index 6fd607587..9938ae48f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h @@ -881,6 +881,7 @@ struct amdgpu_device { /* enable runtime pm on the device */ bool in_runpm; bool has_pr3; + bool runpm_active; bool ucode_sysfs_en; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index ac336594b..ed205352f 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -947,6 +947,10 @@ bool amdgpu_device_skip_hw_access(struct amdgpu_device *adev) if (adev->no_hw_access) return true; + if (unlikely(!READ_ONCE(adev->runpm_active))) { + WARN_RATELIMIT(1, "%s: register access while powered off\n", dev_name(adev->dev)); + return true; + } #ifdef CONFIG_LOCKDEP /* * This is a bit complicated to understand, so worth a comment. What we assert @@ -2029,6 +2033,7 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev) int i, r; amdgpu_device_enable_virtual_display(adev); + adev->runpm_active = true; if (amdgpu_sriov_vf(adev)) { /* diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index 3978ed284..d1b0c6c73 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -2935,6 +2935,9 @@ static int amdgpu_pmops_runtime_suspend(struct device *dev) amdgpu_device_baco_enter(adev); } + if (adev->pm.rpm_mode == AMDGPU_RUNPM_GMUX) + WRITE_ONCE(adev->runpm_active, false); + dev_dbg(&pdev->dev, "asic/device is runtime suspended\n"); return 0; @@ -2963,6 +2966,8 @@ static int amdgpu_pmops_runtime_resume(struct device *dev) if (adev->pm.rpm_mode == AMDGPU_RUNPM_NONE) return -EINVAL; + WRITE_ONCE(adev->runpm_active, true); + /* Avoids registers access if device is physically gone */ if (!pci_device_is_present(adev->pdev)) adev->no_hw_access = true; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c index 7468855c1..64eba8a97 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_reg_access.c @@ -594,6 +594,9 @@ u32 amdgpu_device_indirect_rreg(struct amdgpu_device *adev, u32 reg_addr) void __iomem *pcie_data_offset; u32 r; + if (amdgpu_device_skip_hw_access(adev)) + return 0; + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); @@ -617,6 +620,9 @@ u32 amdgpu_device_indirect_rreg_ext(struct amdgpu_device *adev, u64 reg_addr) void __iomem *pcie_index_hi_offset; void __iomem *pcie_data_offset; + if (amdgpu_device_skip_hw_access(adev)) + return 0; + if (unlikely(!adev->nbio.funcs)) { pcie_index = AMDGPU_PCIE_INDEX_FALLBACK; pcie_data = AMDGPU_PCIE_DATA_FALLBACK; @@ -677,6 +683,9 @@ u64 amdgpu_device_indirect_rreg64(struct amdgpu_device *adev, u32 reg_addr) void __iomem *pcie_data_offset; u64 r; + if (amdgpu_device_skip_hw_access(adev)) + return 0; + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); @@ -706,6 +715,9 @@ u64 amdgpu_device_indirect_rreg64_ext(struct amdgpu_device *adev, u64 reg_addr) void __iomem *pcie_data_offset; u64 r; + if (amdgpu_device_skip_hw_access(adev)) + return 0; + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) @@ -762,6 +774,9 @@ void amdgpu_device_indirect_wreg(struct amdgpu_device *adev, u32 reg_addr, void __iomem *pcie_index_offset; void __iomem *pcie_data_offset; + if (amdgpu_device_skip_hw_access(adev)) + return; + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); @@ -784,6 +799,9 @@ void amdgpu_device_indirect_wreg_ext(struct amdgpu_device *adev, u64 reg_addr, void __iomem *pcie_index_hi_offset; void __iomem *pcie_data_offset; + if (amdgpu_device_skip_hw_access(adev)) + return; + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) @@ -832,6 +850,9 @@ void amdgpu_device_indirect_wreg64(struct amdgpu_device *adev, u32 reg_addr, void __iomem *pcie_index_offset; void __iomem *pcie_data_offset; + if (amdgpu_device_skip_hw_access(adev)) + return; + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); @@ -861,6 +882,9 @@ void amdgpu_device_indirect_wreg64_ext(struct amdgpu_device *adev, u64 reg_addr, void __iomem *pcie_index_hi_offset; void __iomem *pcie_data_offset; + if (amdgpu_device_skip_hw_access(adev)) + return; + pcie_index = adev->nbio.funcs->get_pcie_index_offset(adev); pcie_data = adev->nbio.funcs->get_pcie_data_offset(adev); if ((reg_addr >> 32) && (adev->nbio.funcs->get_pcie_index_hi_offset)) -- 2.55.0