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Sat, 14 Nov 2026 15:37:33 -0800 (PST) Received: from ryzen.lan ([2601:644:8000:37f::e34]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8bed2d0f473sm2306372b3a.53.2026.11.14.15.37.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Nov 2026 15:37:32 -0800 (PST) From: Rosen Penev To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Thomas Bogendoerfer , Thomas Gleixner Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Radu Rendec , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 3/4] irqchip/ath79-misc: convert to a platform driver Date: Sat, 14 Nov 2026 15:37:17 -0800 Message-ID: <20261114233718.86520-4-rosenp@gmail.com> X-Mailer: git-send-email 2.56.1 In-Reply-To: <20261114233718.86520-1-rosenp@gmail.com> References: <20261114233718.86520-1-rosenp@gmail.com> X-Mailing-List: linux-perf-users@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The MISC interrupt controller is cascaded from a CPU interrupt, and its users are all platform devices, which defer their probe until it is available. The performance counter interrupt, the only one needed before the early initcalls, is now mapped on demand. Probe the controller as a platform driver, and use device-managed resources, which also fixes the leak of the register mapping when the irq domain cannot be created. The driver now probes after plat_time_init(), which on QCA956x and TP9343 enables the MIPS timer interrupt in the MISC controller, without which there are no jiffies. Keep that enable bit when disabling the other interrupts, which leaves the register as it was with the old init order. Signed-off-by: Rosen Penev --- drivers/irqchip/irq-ath79-misc.c | 90 ++++++++++++++++---------------- 1 file changed, 44 insertions(+), 46 deletions(-) diff --git a/drivers/irqchip/irq-ath79-misc.c b/drivers/irqchip/irq-ath79-misc.c index 5cedea5234e0..e69d4eca929f 100644 --- a/drivers/irqchip/irq-ath79-misc.c +++ b/drivers/irqchip/irq-ath79-misc.c @@ -12,8 +12,9 @@ #include #include -#include -#include +#include +#include +#include #include @@ -22,6 +23,7 @@ #define ATH79_MISC_IRQ_COUNT 32 #define ATH79_MISC_PERF_IRQ 5 +#define ATH79_MISC_SI_TIMERINT BIT(28) static struct irq_domain *ath79_misc_domain; @@ -124,65 +126,61 @@ static const struct irq_domain_ops misc_irq_domain_ops = { .map = misc_map, }; -static void __init ath79_misc_intc_domain_init( - struct irq_domain *domain, int irq) -{ - void __iomem *base = domain->host_data; - - /* Disable and clear all interrupts */ - __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE); - __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); - - irq_set_chained_handler_and_data(irq, ath79_misc_irq_handler, domain); -} - -static int __init ath79_misc_intc_of_init( - struct device_node *node, struct device_node *parent) +static int ath79_misc_intc_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct irq_domain *domain; void __iomem *base; + u32 enable; int irq; - irq = irq_of_parse_and_map(node, 0); - if (!irq) { - pr_err("Failed to get MISC IRQ\n"); - return -EINVAL; - } - - base = of_iomap(node, 0); - if (!base) { - pr_err("Failed to get MISC IRQ registers\n"); - return -ENOMEM; - } - - domain = irq_domain_create_linear(of_fwnode_handle(node), ATH79_MISC_IRQ_COUNT, - &misc_irq_domain_ops, base); - if (!domain) { - pr_err("Failed to add MISC irqdomain\n"); - return -EINVAL; - } + irq = platform_get_irq(pdev, 0); + if (irq < 0) + return irq; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + domain = devm_irq_domain_create_linear(dev, dev_fwnode(dev), + ATH79_MISC_IRQ_COUNT, + &misc_irq_domain_ops, base); + if (!domain) + return dev_err_probe(dev, -ENOMEM, "failed to add the irq domain\n"); + + /* + * Disable and clear all interrupts, except the MIPS timer interrupt: + * plat_time_init() enables it on QCA956x and TP9343, which have no + * jiffies without it, and that runs before this driver probes. + */ + enable = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE); + __raw_writel(enable & ATH79_MISC_SI_TIMERINT, + base + AR71XX_RESET_REG_MISC_INT_ENABLE); + __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_STATUS); - ath79_misc_intc_domain_init(domain, irq); + irq_set_chained_handler_and_data(irq, ath79_misc_irq_handler, domain); ath79_misc_domain = domain; + return 0; } -static int __init ar7100_misc_intc_of_init( - struct device_node *node, struct device_node *parent) +static int ar7100_misc_intc_probe(struct platform_device *pdev, + struct device_node *parent) { ath79_misc_irq_chip.irq_mask_ack = ar71xx_misc_irq_mask; - return ath79_misc_intc_of_init(node, parent); + return ath79_misc_intc_probe(pdev); } -IRQCHIP_DECLARE(ar7100_misc_intc, "qca,ar7100-misc-intc", - ar7100_misc_intc_of_init); - -static int __init ar7240_misc_intc_of_init( - struct device_node *node, struct device_node *parent) +static int ar7240_misc_intc_probe(struct platform_device *pdev, + struct device_node *parent) { ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack; - return ath79_misc_intc_of_init(node, parent); + return ath79_misc_intc_probe(pdev); } -IRQCHIP_DECLARE(ar7240_misc_intc, "qca,ar7240-misc-intc", - ar7240_misc_intc_of_init); +IRQCHIP_PLATFORM_DRIVER_BEGIN(ath79_misc_intc) +IRQCHIP_MATCH("qca,ar7100-misc-intc", ar7100_misc_intc_probe) +IRQCHIP_MATCH("qca,ar7240-misc-intc", ar7240_misc_intc_probe) +IRQCHIP_PLATFORM_DRIVER_END(ath79_misc_intc) +MODULE_DESCRIPTION("Atheros AR71xx/AR724x/AR913x MISC interrupt controller"); +MODULE_LICENSE("GPL"); -- 2.56.1