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[2001:4c4e:24ef:f00:8016:2cdb:5b2d:facf]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-493c635c41dsm89611295e9.5.2026.07.02.05.47.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jul 2026 05:47:27 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org, Alexander.Deucher@amd.com, Natalie Vock , Amir Shetaia , Marek =?UTF-8?B?T2zFocOhaw==?= , Mario Limonciello , Tvrtko Ursulin , Felix Kuehling , Lijo Lazar , Siwei He , Philip Yang , Mukul Joshi , Christian =?UTF-8?B?S8O2bmln?= Subject: Re: [PATCH 14/14] drm/amdgpu/ih7.0: Enable retry CAM on Navi 4 dGPUs Date: Thu, 02 Jul 2026 14:47:25 +0200 Message-ID: <20288636.fSG56mABFh@timur-max> In-Reply-To: <15459d84-24fd-404c-b90f-97d2ecfb7af8@amd.com> References: <20260701161721.85681-1-timur.kristof@gmail.com> <5873192.ZASKD2KPVS@timur-max> <15459d84-24fd-404c-b90f-97d2ecfb7af8@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 2026. j=C3=BAlius 2., cs=C3=BCt=C3=B6rt=C3=B6k 14:30:20 k=C3=B6z=C3=A9p-= eur=C3=B3pai ny=C3=A1ri id=C5=91 Christian K=C3=B6nig=20 wrote: > On 7/2/26 13:53, Timur Krist=C3=B3f wrote: > > On 2026. j=C3=BAlius 2., cs=C3=BCt=C3=B6rt=C3=B6k 12:38:12 k=C3=B6z=C3= =A9p-eur=C3=B3pai ny=C3=A1ri id=C5=91 Christian > > K=C3=B6nig>=20 > > wrote: > >> On 7/1/26 18:17, Timur Krist=C3=B3f wrote: > >>> The retry CAM can filter interrupts which occur repeatedly, > >>> such as page fault interrupts when retry faults are enabled. > >>> This makes processing those interrupts much more efficient, > >>> because the CPU won't have to deal with processing the same > >>> interrupt repeatedly. > >>>=20 > >>> Signed-off-by: Timur Krist=C3=B3f > >>> --- > >>>=20 > >>> drivers/gpu/drm/amd/amdgpu/ih_v7_0.c | 3 ++- > >>> 1 file changed, 2 insertions(+), 1 deletion(-) > >>>=20 > >>> diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c > >>> b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c index 291326d2ee8b..ec0919fa82= 54 > >>> 100644 > >>> --- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c > >>> +++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c > >>> @@ -390,7 +390,8 @@ static int ih_v7_0_irq_init(struct amdgpu_device > >>> *adev) > >>>=20 > >>> pci_set_master(adev->pdev); > >>>=20 > >>> - if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) =3D=3D IP_VERSION(7, 1, > >=20 > > 0)) { > >=20 > >>> + if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) =3D=3D IP_VERSION(7, 1,= 0) > >>>=20 > >>> + !(adev->flags & AMD_IS_APU)) { > >>=20 > >> I think the check should be the other way around. > >>=20 > >> In other words we can enable the cam on dGPU or APUs with IP version 7= =2E1 > >> because that one has the CAM as well. > >=20 > > What do you mean by the other way around? > >=20 > > The patch keeps pre-existing behaviour on IH 7.1 and additionally enabl= es > > the retry CAM on dGPUs. The patch makes no functional changes to IH 7.1, > > on that version the retry CAM is always enabled regardless of whether > > it's an APU or dGPU. >=20 > I just wanted to make the logic more readable. In other words: >=20 > if (!(adev->flags & AMD_IS_APU) || > amdgpu_ip_version(adev, OSSSYS_HWIP, 0) =3D=3D IP_VERSION(7, 1, 0)) Thanks, and sorry for the confusion. I'll apply this suggestion to the next version of the series. >=20 > I still need to double check why we have the exception for OSSSYS 7.1. >=20 > Could be that this is for some MI* product, but I'm not 100% sure yet. It was added in commit e06d19420118 I don't know which products have IH 7.1 because the IH block versions are n= ot=20 mentioned in the ASIC info table. I guess IH 7.1 goes with GFX 12.1 but I=20 don't have any way to verify that guess. >=20 > >>> /* Enable IH Retry CAM */ > >>> tmp =3D RREG32_SOC15(OSSSYS, 0, > >=20 > > regIH_RETRY_INT_CAM_CNTL); > >=20 > >>> tmp =3D REG_SET_FIELD(tmp, IH_RETRY_INT_CAM_CNTL, ENABLE, > >=20 > > 1);