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[2001:4c4e:24cd:7200:f6bb:a872:344e:1a32]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f464b7e22sm14773371f8f.25.2026.07.15.03.16.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 03:16:37 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org, Alex Deucher , christian.koenig@amd.com, pierre-eric.pelloux-prayer@amd.com, Natalie Vock , Tvrtko Ursulin Subject: Re: [PATCH 6/9] drm/amdgpu/gfx7: Clean up gfx ring during reset Date: Wed, 15 Jul 2026 12:16:36 +0200 Message-ID: <20288812.fSG56mABFh@timur-max> In-Reply-To: References: <20260713125838.30607-1-timur.kristof@gmail.com> <20260713125838.30607-7-timur.kristof@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 2026. j=C3=BAlius 15., szerda 11:18:19 k=C3=B6z=C3=A9p-eur=C3=B3pai ny= =C3=A1ri id=C5=91 Tvrtko Ursulin=20 wrote: > On 13/07/2026 13:58, Timur Krist=C3=B3f wrote: > > Clear the WPTR and RPTR at ring initialization. > > Additionally clear the ring contents during reset. >=20 > Please add the why part to your commit messages. ;) After a reset, the ring contents could be "dirty" and thus need to be clear= ed=20 to prevent the command processor from executing packets left over in the ri= ng=20 from before the reset. I think this is obvious, but I'm happy to add some t= ext=20 to the commit message to explain it more. >=20 > Cover letter mentions the series is reworking to match gfx7 to gfx8 but > I looked in drm-tip and amd-staging-drm-next and > gfx_v8_0_cp_gfx_resume() does not yet have these changes. The GFX8 code does have this: =46or graphics queues: In gfx_v8_0_cp_gfx_resume() it also sets wptr =3D 0; and calls=20 amdgpu_ring_clear_ring() unconditionally. This is actually not needed durin= g=20 first initialization because the amdgpu_ring_init() called from=20 gfx_v8_0_sw_init() already clears the ring, which is why I call the clear=20 conditionally on GFX6-7. I could of course change the GFX6-7 code to also c= all=20 it unconditionally though for the sake of simplicity and consistency. (It is missing the atomic things though. I think it should have that too.) =46or compute queues: In gfx_v8_0_kcq_init_queue() it clears the wptr, also the wptr_cpu_addr and= =20 also calls amdgpu_ring_clear_ring(). >=20 > > Signed-off-by: Timur Krist=C3=B3f > > --- > >=20 > > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 9 ++++++++- > > 1 file changed, 8 insertions(+), 1 deletion(-) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index a93cc02c3400..915612628f9a > > 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > @@ -2546,8 +2546,14 @@ static int gfx_v7_0_cp_gfx_resume(struct > > amdgpu_device *adev)>=20 > > WREG32(mmSCRATCH_ADDR, 0); > > =09 > > /* ring 0 - compute and gfx */ > >=20 > > - /* Set ring buffer size */ > >=20 > > ring =3D &adev->gfx.gfx_ring[0]; > >=20 > > + atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); > > + atomic64_set((atomic64_t *)ring->rptr_cpu_addr, 0); >=20 > One day we need to fix this whole atomic64 situation. What is the situation that needs to be fixed? >=20 > > + > > + if (amdgpu_in_reset(adev)) > > + amdgpu_ring_clear_ring(ring); > > + > > + /* Set ring buffer size */ > >=20 > > rb_bufsz =3D order_base_2(ring->ring_size / 8); > > tmp =3D (order_base_2(AMDGPU_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; > > =20 > > #ifdef __BIG_ENDIAN > >=20 > > @@ -2559,6 +2565,7 @@ static int gfx_v7_0_cp_gfx_resume(struct > > amdgpu_device *adev)>=20 > > WREG32(mmCP_RB0_CNTL, tmp | CP_RB0_CNTL__RB_RPTR_WR_ENA_MASK); > > ring->wptr =3D 0; > > WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); > >=20 > > + WREG32(mmCP_RB0_RPTR, lower_32_bits(ring->wptr)); > >=20 > > /* set the wb address whether it's enabled or not */ > > rptr_addr =3D ring->rptr_gpu_addr;