diff for duplicates of <20493371.uo7oml5YRN@avalon> diff --git a/a/1.txt b/N1/1.txt index a7e6e7a..2b5be57 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -63,7 +63,7 @@ On Wednesday 26 February 2014 16:33:20 Simon Horman wrote: > + }; > + > + /* Special CPG clocks */ -> + cpg_clocks: cpg_clocks@0xe6150000 { +> + cpg_clocks: cpg_clocks at 0xe6150000 { > + compatible = "renesas,r8a7779-cpg-clocks"; > + reg = <0 0xe6150000 0 0x1000>; > + clocks = <&extal_clk>; @@ -134,7 +134,8 @@ clks1 ? > + R8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2 > + R8A7779_CLK_I2C1 R8A7779_CLK_I2C0 > + >; -> + clock-output-names > + "hspi", "tmu00", "tmu01", +> + clock-output-names = +> + "hspi", "tmu00", "tmu01", > + "tmu02", "scif5", "scif4", The clock names should be tmu0, tmu1 and tmu2, not tmu00, tmu01 and tmu02. @@ -166,7 +167,8 @@ Please verify the clock parents here as well. > + R8A7779_CLK_ETHER R8A7779_CLK_SATA > + R8A7779_CLK_PCIE R8A7779_CLK_VIN3 > + >; -> + clock-output-names > + "ehci0", "ohci0", +> + clock-output-names = +> + "ehci0", "ohci0", > + "ehci1", "ohci1", > + "du", "vin2", > + "vin1", "vin0", @@ -190,7 +192,8 @@ Aren't the MMC and SDHI parent clocks clks4 ? > + R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 > + R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 > + >; -> + clock-output-names > + "sdhi3", "sdhi2", +> + clock-output-names = +> + "sdhi3", "sdhi2", > + "sdhi1", "sdhi0", > + "mmc1", "mmc0"; > + }; diff --git a/a/content_digest b/N1/content_digest index ef3aef6..e3c9fb0 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,8 @@ "ref\01393400016-23433-1-git-send-email-horms+renesas@verge.net.au\0" "ref\01393400016-23433-5-git-send-email-horms+renesas@verge.net.au\0" - "From\0Laurent Pinchart <laurent.pinchart@ideasonboard.com>\0" - "Subject\0Re: [PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks\0" - "Date\0Wed, 26 Feb 2014 13:15:14 +0000\0" + "From\0laurent.pinchart@ideasonboard.com (Laurent Pinchart)\0" + "Subject\0[PATCH v3 04/20] ARM: shmobile: r8a7779: Add clocks\0" + "Date\0Wed, 26 Feb 2014 14:15:14 +0100\0" "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" @@ -71,7 +71,7 @@ "> +\t\t};\n" "> +\n" "> +\t\t/* Special CPG clocks */\n" - "> +\t\tcpg_clocks: cpg_clocks@0xe6150000 {\n" + "> +\t\tcpg_clocks: cpg_clocks at 0xe6150000 {\n" "> +\t\t\tcompatible = \"renesas,r8a7779-cpg-clocks\";\n" "> +\t\t\treg = <0 0xe6150000 0 0x1000>;\n" "> +\t\t\tclocks = <&extal_clk>;\n" @@ -142,7 +142,8 @@ "> +\t\t\t\tR8A7779_CLK_SCIF0 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2\n" "> +\t\t\t\tR8A7779_CLK_I2C1 R8A7779_CLK_I2C0\n" "> +\t\t\t>;\n" - "> +\t\t\tclock-output-names > +\t\t\t\t\"hspi\", \"tmu00\", \"tmu01\",\n" + "> +\t\t\tclock-output-names =\n" + "> +\t\t\t\t\"hspi\", \"tmu00\", \"tmu01\",\n" "> +\t\t\t\t\"tmu02\", \"scif5\", \"scif4\",\n" "\n" "The clock names should be tmu0, tmu1 and tmu2, not tmu00, tmu01 and tmu02.\n" @@ -174,7 +175,8 @@ "> +\t\t\t\tR8A7779_CLK_ETHER R8A7779_CLK_SATA\n" "> +\t\t\t\tR8A7779_CLK_PCIE R8A7779_CLK_VIN3\n" "> +\t\t\t>;\n" - "> +\t\t\tclock-output-names > +\t\t\t\t\"ehci0\", \"ohci0\",\n" + "> +\t\t\tclock-output-names =\n" + "> +\t\t\t\t\"ehci0\", \"ohci0\",\n" "> +\t\t\t\t\"ehci1\", \"ohci1\",\n" "> +\t\t\t\t\"du\", \"vin2\",\n" "> +\t\t\t\t\"vin1\", \"vin0\",\n" @@ -198,7 +200,8 @@ "> +\t\t\t\tR8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0\n" "> +\t\t\t\tR8A7779_CLK_MMC1 R8A7779_CLK_MMC0\n" "> +\t\t\t>;\n" - "> +\t\t\tclock-output-names > +\t\t\t\t\"sdhi3\", \"sdhi2\",\n" + "> +\t\t\tclock-output-names =\n" + "> +\t\t\t\t\"sdhi3\", \"sdhi2\",\n" "> +\t\t\t\t\"sdhi1\", \"sdhi0\",\n" "> +\t\t\t\t\"mmc1\", \"mmc0\";\n" "> +\t\t};\n" @@ -210,4 +213,4 @@ "\n" Laurent Pinchart -5663e75617066c1aa159b4aacd2b172a2f432b8e23ad95f331c1f93931d9c53b +05c16e72446a1fcabdd86ef752b58ad82ddda4450ab084e3d0a6736d743c03ba
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