[PATCH] net/mlx5: fix offset handling in mlx5_aso_cnt_sq_enqueue_burst

[Mohand Alrasheed <mrasheed@wirefilter.com>]

From 9ca4302dd93461a7b01ad05af82ee2bcadf47675 Mon Sep 17 00:00:00 2001
From: Mohand Alrasheed <mrasheed@wirefilter.com>
Date: Mon, 5 Jan 2026 15:44:25 +0300
Subject: [PATCH] net/mlx5: fix offset handling in
 mlx5_aso_cnt_sq_enqueue_burst

mlx5_aso_cnt_sq_enqueue_burst() selects the ASO counter block using
dcs_id_base/4 and ignores the batch offset. This causes every batch to
target the first counter block, leading to counter aliasing (e.g. 2^16
matches 0).

This patch selects the counter block using the offset-adjusted index.

Reproducible example: https://github.com/Hawzen/rte-flow-async-profiling/blob/5e654e3a8a0414a5fa8ed43274195f180760f0b5/examples/flow_filtering/reproduce.md

Fixes: 4d368e1da3a453cbcac620e8844c0300b2f45cfa
Cc: jackmin@nvidia.com
Cc: stable@dpdk.org
---
 drivers/net/mlx5/mlx5_flow_aso.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/mlx5/mlx5_flow_aso.c b/drivers/net/mlx5/mlx5_flow_aso.c
index feca8c3e89..a232289024 100644
--- a/drivers/net/mlx5/mlx5_flow_aso.c
+++ b/drivers/net/mlx5/mlx5_flow_aso.c
@@ -1877,6 +1877,7 @@ mlx5_aso_cnt_sq_enqueue_burst(struct mlx5_hws_cnt_pool *cpool,
 	sq->elts[0].burst_size = max;
 	ctrl_gen_id = dcs_id_base;
 	ctrl_gen_id /= 4;
+	ctrl_gen_id += offset / 4;
 	do {
 		ccntid = upper_offset - max * 4;
 		wqe = &sq->sq_obj.aso_wqes[sq->head & mask];
--
2.39.5