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Wed, 4 Nov 2026 11:38:03 +0000 (GMT) Received: from epcpadp2new (unknown [182.195.40.142]) by epsnrtp01.localdomain (Postfix) with ESMTP id 4jKNjR3KrDz6B9m4; Wed, 4 Nov 2026 11:38:03 +0000 (GMT) Received: from epsmtip1.samsung.com (unknown [182.195.34.30]) by epcas5p3.samsung.com (KnoxPortal) with ESMTPA id 20261104113020epcas5p312cb465740fb11b04b576aa6d026a81f~k1CgjSlA51814518145epcas5p3A; Wed, 4 Nov 2026 11:30:20 +0000 (GMT) Received: from unvme-SYS-221H-TN24R.samsungds.net (unknown [107.99.40.127]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20261104113017epsmtip10536a07f8b7f0d7456c9d5eace70cd7b~k1CePRkmm2317923179epsmtip1k; Wed, 4 Nov 2026 11:30:17 +0000 (GMT) From: Shrihari E S To: jic23@kernel.org, junjie.cao@linux.dev, linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org, qemu-devel@nongnu.org, anisa.su887@gmail.com, mst@redhat.com, marcel.apfelbaum@gmail.com Cc: shrihari.s@samsung.com, arun.george@samsung.com, cpgs@samsung.com, dave@stgolabs.net, dongjoo.seo1@samsung.com, gost.dev@samsung.com, s.neeraj@samsung.com, vikash.k5@samsung.com, anisa.su@samsung.com, junjie.cao@intel.com Subject: [PATCH qemu v1 2/8] hw/pci: Move 'x-256b-flit' property from cxl_root_port to pcie_root_port Date: Wed, 4 Nov 2026 17:22:36 +0530 Message-Id: <2052256418.81793792283466.JavaMail.epsvc@epcpadp2new> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261104115242.2035807-1-shrihari.s@samsung.com> X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CMS-MailID: 20261104113020epcas5p312cb465740fb11b04b576aa6d026a81f X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P X-CPGSPASS: Y X-Hop-Count: 3 X-CMS-RootMailID: 20261104113020epcas5p312cb465740fb11b04b576aa6d026a81f References: <20261104115242.2035807-1-shrihari.s@samsung.com> Relocate the 'x-256b-flit' property from cxl_root_port to its parent pcie_root_port so that all root port types inherit the property. The cxl_root_port and cxl_downstream_port no longer carry a local property definition; the property is inherited from pcie_root_port and PCIEPort respectively. Signed-off-by: Shrihari E S --- hw/pci-bridge/cxl_root_port.c | 1 - hw/pci-bridge/pcie_root_port.c | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 01463dbb07..e82685d1ab 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -237,7 +237,6 @@ static const Property gen_rp_props[] = { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_32), - DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, false), }; static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr, diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index fe3ced5685..bc173dbf30 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -152,6 +152,7 @@ static const Property rp_props[] = { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), DEFINE_PROP_BOOL("disable-acs", PCIESlot, disable_acs, false), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, false), }; static void rp_instance_post_init(Object *obj) -- 2.34.1