From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jae Hyun Yoo Date: Wed, 15 Jan 2020 17:44:51 -0800 Subject: [PATCH 1/2] clk: aspeed: add critical clock setting logic In-Reply-To: References: <20200115212639.4998-1-jae.hyun.yoo@linux.intel.com> <20200115212639.4998-2-jae.hyun.yoo@linux.intel.com> Message-ID: <2088ff06-2bf0-b158-6df7-17171dde4e03@linux.intel.com> List-Id: To: linux-aspeed@lists.ozlabs.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit On 1/15/2020 5:38 PM, Joel Stanley wrote: > On Wed, 15 Jan 2020 at 21:25, Jae Hyun Yoo wrote: >> >> This commit adds critical clock setting logic that applies >> CLK_IS_CRITICAL flag if it detects 'clock-critical' property in >> device tree. >> >> Signed-off-by: Jae Hyun Yoo >> --- >> drivers/clk/clk-aspeed.c | 5 ++++- >> 1 file changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c >> index 411ff5fb2c07..d22eeb574ede 100644 >> --- a/drivers/clk/clk-aspeed.c >> +++ b/drivers/clk/clk-aspeed.c >> @@ -541,8 +541,11 @@ static int aspeed_clk_probe(struct platform_device *pdev) >> >> for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) { >> const struct aspeed_gate_data *gd = &aspeed_gates[i]; >> + unsigned long flags = gd->flags; >> u32 gate_flags; >> >> + of_clk_detect_critical(pdev->dev.of_node, i, &flags); > > This makes sense to me. > >> + >> /* Special case: the USB port 1 clock (bit 14) is always >> * working the opposite way from the other ones. >> */ >> @@ -550,7 +553,7 @@ static int aspeed_clk_probe(struct platform_device *pdev) >> hw = aspeed_clk_hw_register_gate(dev, >> gd->name, >> gd->parent_name, >> - gd->flags, >> + flags, > > For completeness should we make this > > flags | gd->flags Not needed. of_clk_detect_critical uses OR operation inside. >> map, >> gd->clock_idx, >> gd->reset_idx, >> -- >> 2.17.1 >> From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7BB78C32771 for ; Thu, 16 Jan 2020 01:44:53 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 510BA24656 for ; Thu, 16 Jan 2020 01:44:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730241AbgAPBox (ORCPT ); Wed, 15 Jan 2020 20:44:53 -0500 Received: from mga05.intel.com ([192.55.52.43]:53353 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730200AbgAPBow (ORCPT ); Wed, 15 Jan 2020 20:44:52 -0500 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 15 Jan 2020 17:44:52 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,323,1574150400"; d="scan'208";a="225793657" Received: from yoojae-mobl1.amr.corp.intel.com (HELO [10.7.153.147]) ([10.7.153.147]) by orsmga003.jf.intel.com with ESMTP; 15 Jan 2020 17:44:51 -0800 Subject: Re: [PATCH 1/2] clk: aspeed: add critical clock setting logic To: Joel Stanley Cc: linux-aspeed , Stephen Boyd , Michael Turquette , OpenBMC Maillist , Andrew Jeffery , linux-clk@vger.kernel.org References: <20200115212639.4998-1-jae.hyun.yoo@linux.intel.com> <20200115212639.4998-2-jae.hyun.yoo@linux.intel.com> From: Jae Hyun Yoo Message-ID: <2088ff06-2bf0-b158-6df7-17171dde4e03@linux.intel.com> Date: Wed, 15 Jan 2020 17:44:51 -0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org On 1/15/2020 5:38 PM, Joel Stanley wrote: > On Wed, 15 Jan 2020 at 21:25, Jae Hyun Yoo wrote: >> >> This commit adds critical clock setting logic that applies >> CLK_IS_CRITICAL flag if it detects 'clock-critical' property in >> device tree. >> >> Signed-off-by: Jae Hyun Yoo >> --- >> drivers/clk/clk-aspeed.c | 5 ++++- >> 1 file changed, 4 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c >> index 411ff5fb2c07..d22eeb574ede 100644 >> --- a/drivers/clk/clk-aspeed.c >> +++ b/drivers/clk/clk-aspeed.c >> @@ -541,8 +541,11 @@ static int aspeed_clk_probe(struct platform_device *pdev) >> >> for (i = 0; i < ARRAY_SIZE(aspeed_gates); i++) { >> const struct aspeed_gate_data *gd = &aspeed_gates[i]; >> + unsigned long flags = gd->flags; >> u32 gate_flags; >> >> + of_clk_detect_critical(pdev->dev.of_node, i, &flags); > > This makes sense to me. > >> + >> /* Special case: the USB port 1 clock (bit 14) is always >> * working the opposite way from the other ones. >> */ >> @@ -550,7 +553,7 @@ static int aspeed_clk_probe(struct platform_device *pdev) >> hw = aspeed_clk_hw_register_gate(dev, >> gd->name, >> gd->parent_name, >> - gd->flags, >> + flags, > > For completeness should we make this > > flags | gd->flags Not needed. of_clk_detect_critical uses OR operation inside. >> map, >> gd->clock_idx, >> gd->reset_idx, >> -- >> 2.17.1 >>