From mboxrd@z Thu Jan 1 00:00:00 1970 From: Samuel Holland Date: Wed, 4 Sep 2024 09:57:13 -0500 Subject: [PATCH v4 09/10] RISC-V: KVM: Allow Smnpm and Ssnpm extensions for guests In-Reply-To: References: <20240829010151.2813377-1-samuel.holland@sifive.com> <20240829010151.2813377-10-samuel.holland@sifive.com> Message-ID: <20ab0fa2-d5dd-446d-9fff-a3ef82e8db35@sifive.com> List-Id: To: kvm-riscv@lists.infradead.org MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Hi Anup, On 2024-09-04 9:45 AM, Anup Patel wrote: > On Wed, Sep 4, 2024 at 8:01?PM Samuel Holland wrote: >> On 2024-09-04 7:17 AM, Anup Patel wrote: >>> On Thu, Aug 29, 2024 at 6:32?AM Samuel Holland >>> wrote: >>>> >>>> The interface for controlling pointer masking in VS-mode is henvcfg.PMM, >>>> which is part of the Ssnpm extension, even though pointer masking in >>>> HS-mode is provided by the Smnpm extension. As a result, emulating Smnpm >>>> in the guest requires (only) Ssnpm on the host. >>>> >>>> Since the guest configures Smnpm through the SBI Firmware Features >>>> interface, the extension can be disabled by failing the SBI call. Ssnpm >>>> cannot be disabled without intercepting writes to the senvcfg CSR. >>>> >>>> Signed-off-by: Samuel Holland >>>> --- >>>> >>>> (no changes since v2) >>>> >>>> Changes in v2: >>>> - New patch for v2 >>>> >>>> arch/riscv/include/uapi/asm/kvm.h | 2 ++ >>>> arch/riscv/kvm/vcpu_onereg.c | 3 +++ >>>> 2 files changed, 5 insertions(+) >>>> >>>> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h >>>> index e97db3296456..4f24201376b1 100644 >>>> --- a/arch/riscv/include/uapi/asm/kvm.h >>>> +++ b/arch/riscv/include/uapi/asm/kvm.h >>>> @@ -175,6 +175,8 @@ enum KVM_RISCV_ISA_EXT_ID { >>>> KVM_RISCV_ISA_EXT_ZCF, >>>> KVM_RISCV_ISA_EXT_ZCMOP, >>>> KVM_RISCV_ISA_EXT_ZAWRS, >>>> + KVM_RISCV_ISA_EXT_SMNPM, >>>> + KVM_RISCV_ISA_EXT_SSNPM, >>>> KVM_RISCV_ISA_EXT_MAX, >>>> }; >>>> >>>> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c >>>> index b319c4c13c54..6f833ec2344a 100644 >>>> --- a/arch/riscv/kvm/vcpu_onereg.c >>>> +++ b/arch/riscv/kvm/vcpu_onereg.c >>>> @@ -34,9 +34,11 @@ static const unsigned long kvm_isa_ext_arr[] = { >>>> [KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m, >>>> [KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v, >>>> /* Multi letter extensions (alphabetically sorted) */ >>>> + [KVM_RISCV_ISA_EXT_SMNPM] = RISCV_ISA_EXT_SSNPM, >>> >>> Why not use KVM_ISA_EXT_ARR() macro here ? >> >> Because the extension name in the host does not match the extension name in the >> guest. Pointer masking for HS mode is provided by Smnpm. Pointer masking for VS >> mode is provided by Ssnpm at the hardware level, but this needs to appear to the >> guest as if Smnpm was implemented, since the guest thinks it is running on bare >> metal. > > Okay, makes sense. > >> >>>> KVM_ISA_EXT_ARR(SMSTATEEN), >>>> KVM_ISA_EXT_ARR(SSAIA), >>>> KVM_ISA_EXT_ARR(SSCOFPMF), >>>> + KVM_ISA_EXT_ARR(SSNPM), >>>> KVM_ISA_EXT_ARR(SSTC), >>>> KVM_ISA_EXT_ARR(SVINVAL), >>>> KVM_ISA_EXT_ARR(SVNAPOT), >>>> @@ -129,6 +131,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) >>>> case KVM_RISCV_ISA_EXT_M: >>>> /* There is not architectural config bit to disable sscofpmf completely */ >>>> case KVM_RISCV_ISA_EXT_SSCOFPMF: >>>> + case KVM_RISCV_ISA_EXT_SSNPM: >>> >>> Why not add KVM_RISCV_ISA_EXT_SMNPM here ? >>> >>> Disabling Smnpm from KVM user space is very different from >>> disabling Smnpm from Guest using SBI FWFT extension. >> >> Until a successful SBI FWFT call to KVM to enable pointer masking for VS mode, >> the existence of Smnpm has no visible effect on the guest. So failing the SBI >> call is sufficient to pretend that the hardware does not support Smnpm. >> >>> The KVM user space should always add Smnpm in the >>> Guest ISA string whenever the Host ISA string has it. >> >> I disagree. Allowing userspace to disable extensions is useful for testing and >> to support migration to hosts which do not support those extensions. So I would >> only add extensions to this list if there is no possible way to disable them. > > I am not saying to disallow KVM user space disabling Smnpm. Then I'm confused. This is the "return false;" switch case inside kvm_riscv_vcpu_isa_disable_allowed(). If I add KVM_RISCV_ISA_EXT_SMNPM here, then (unless I am misreading the code) I am disallowing KVM userspace from disabling Smnpm in the guest (i.e. preventing KVM userspace from removing Smnpm from the guest ISA string). If that is not desired, then why do you suggest I add KVM_RISCV_ISA_EXT_SMNPM here? > The presence of Smnpm in ISA only means that it is present in HW > but it needs to be explicitly configured/enabled using SBI FWFT. > > KVM user space can certainly disable extensions by not adding it to > ISA string based on the KVMTOOL/QEMU-KVM command line option. > Additionally, when SBI FWFT is added to KVM RISC-V. It will have its > own way to explicitly disable firmware features from KVM user space. I think we agree on this, but your explanation here appears to conflict with your suggested code change. Apologies if I'm missing something. Regards, Samuel >>> The Guest must explicitly use SBI FWFT to enable >>> Smnpm only after it sees Smnpm in ISA string. >> >> Yes, exactly, and the purpose of not including Smnpm in the switch case here is >> so that KVM user space can control whether or not it appears in the ISA string. >> >> Regards, >> Samuel >> >>>> case KVM_RISCV_ISA_EXT_SSTC: >>>> case KVM_RISCV_ISA_EXT_SVINVAL: >>>> case KVM_RISCV_ISA_EXT_SVNAPOT: >>>> -- >>>> 2.45.1 >>>> >>>> >>>> _______________________________________________ >>>> linux-riscv mailing list >>>> linux-riscv at lists.infradead.org >>>> http://lists.infradead.org/mailman/listinfo/linux-riscv >>> >>> Regards, >>> Anup >> > > Regards, > Anup From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A36A6CD4853 for ; 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Wed, 04 Sep 2024 07:57:15 -0700 (PDT) Received: from [100.64.0.1] ([147.124.94.167]) by smtp.gmail.com with ESMTPSA id 8926c6da1cb9f-4ced2e17ba7sm3122962173.77.2024.09.04.07.57.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 04 Sep 2024 07:57:15 -0700 (PDT) Message-ID: <20ab0fa2-d5dd-446d-9fff-a3ef82e8db35@sifive.com> Date: Wed, 4 Sep 2024 09:57:13 -0500 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 09/10] RISC-V: KVM: Allow Smnpm and Ssnpm extensions for guests To: Anup Patel Cc: Anup Patel , Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, Conor Dooley , kasan-dev@googlegroups.com, Atish Patra , Evgenii Stepanov , Krzysztof Kozlowski , Rob Herring , "Kirill A . Shutemov" , kvm-riscv@lists.infradead.org References: <20240829010151.2813377-1-samuel.holland@sifive.com> <20240829010151.2813377-10-samuel.holland@sifive.com> From: Samuel Holland Content-Language: en-US In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240904_075717_214848_B7D32470 X-CRM114-Status: GOOD ( 28.52 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org SGkgQW51cCwKCk9uIDIwMjQtMDktMDQgOTo0NSBBTSwgQW51cCBQYXRlbCB3cm90ZToKPiBPbiBX ZWQsIFNlcCA0LCAyMDI0IGF0IDg6MDHigK9QTSBTYW11ZWwgSG9sbGFuZCA8c2FtdWVsLmhvbGxh bmRAc2lmaXZlLmNvbT4gd3JvdGU6Cj4+IE9uIDIwMjQtMDktMDQgNzoxNyBBTSwgQW51cCBQYXRl bCB3cm90ZToKPj4+IE9uIFRodSwgQXVnIDI5LCAyMDI0IGF0IDY6MzLigK9BTSBTYW11ZWwgSG9s bGFuZAo+Pj4gPHNhbXVlbC5ob2xsYW5kQHNpZml2ZS5jb20+IHdyb3RlOgo+Pj4+Cj4+Pj4gVGhl IGludGVyZmFjZSBmb3IgY29udHJvbGxpbmcgcG9pbnRlciBtYXNraW5nIGluIFZTLW1vZGUgaXMg aGVudmNmZy5QTU0sCj4+Pj4gd2hpY2ggaXMgcGFydCBvZiB0aGUgU3NucG0gZXh0ZW5zaW9uLCBl dmVuIHRob3VnaCBwb2ludGVyIG1hc2tpbmcgaW4KPj4+PiBIUy1tb2RlIGlzIHByb3ZpZGVkIGJ5 IHRoZSBTbW5wbSBleHRlbnNpb24uIEFzIGEgcmVzdWx0LCBlbXVsYXRpbmcgU21ucG0KPj4+PiBp biB0aGUgZ3Vlc3QgcmVxdWlyZXMgKG9ubHkpIFNzbnBtIG9uIHRoZSBob3N0Lgo+Pj4+Cj4+Pj4g U2luY2UgdGhlIGd1ZXN0IGNvbmZpZ3VyZXMgU21ucG0gdGhyb3VnaCB0aGUgU0JJIEZpcm13YXJl IEZlYXR1cmVzCj4+Pj4gaW50ZXJmYWNlLCB0aGUgZXh0ZW5zaW9uIGNhbiBiZSBkaXNhYmxlZCBi eSBmYWlsaW5nIHRoZSBTQkkgY2FsbC4gU3NucG0KPj4+PiBjYW5ub3QgYmUgZGlzYWJsZWQgd2l0 aG91dCBpbnRlcmNlcHRpbmcgd3JpdGVzIHRvIHRoZSBzZW52Y2ZnIENTUi4KPj4+Pgo+Pj4+IFNp Z25lZC1vZmYtYnk6IFNhbXVlbCBIb2xsYW5kIDxzYW11ZWwuaG9sbGFuZEBzaWZpdmUuY29tPgo+ Pj4+IC0tLQo+Pj4+Cj4+Pj4gKG5vIGNoYW5nZXMgc2luY2UgdjIpCj4+Pj4KPj4+PiBDaGFuZ2Vz IGluIHYyOgo+Pj4+ICAtIE5ldyBwYXRjaCBmb3IgdjIKPj4+Pgo+Pj4+ICBhcmNoL3Jpc2N2L2lu Y2x1ZGUvdWFwaS9hc20va3ZtLmggfCAyICsrCj4+Pj4gIGFyY2gvcmlzY3Yva3ZtL3ZjcHVfb25l cmVnLmMgICAgICB8IDMgKysrCj4+Pj4gIDIgZmlsZXMgY2hhbmdlZCwgNSBpbnNlcnRpb25zKCsp Cj4+Pj4KPj4+PiBkaWZmIC0tZ2l0IGEvYXJjaC9yaXNjdi9pbmNsdWRlL3VhcGkvYXNtL2t2bS5o IGIvYXJjaC9yaXNjdi9pbmNsdWRlL3VhcGkvYXNtL2t2bS5oCj4+Pj4gaW5kZXggZTk3ZGIzMjk2 NDU2Li40ZjI0MjAxMzc2YjEgMTAwNjQ0Cj4+Pj4gLS0tIGEvYXJjaC9yaXNjdi9pbmNsdWRlL3Vh cGkvYXNtL2t2bS5oCj4+Pj4gKysrIGIvYXJjaC9yaXNjdi9pbmNsdWRlL3VhcGkvYXNtL2t2bS5o Cj4+Pj4gQEAgLTE3NSw2ICsxNzUsOCBAQCBlbnVtIEtWTV9SSVNDVl9JU0FfRVhUX0lEIHsKPj4+ PiAgICAgICAgIEtWTV9SSVNDVl9JU0FfRVhUX1pDRiwKPj4+PiAgICAgICAgIEtWTV9SSVNDVl9J U0FfRVhUX1pDTU9QLAo+Pj4+ICAgICAgICAgS1ZNX1JJU0NWX0lTQV9FWFRfWkFXUlMsCj4+Pj4g KyAgICAgICBLVk1fUklTQ1ZfSVNBX0VYVF9TTU5QTSwKPj4+PiArICAgICAgIEtWTV9SSVNDVl9J U0FfRVhUX1NTTlBNLAo+Pj4+ICAgICAgICAgS1ZNX1JJU0NWX0lTQV9FWFRfTUFYLAo+Pj4+ICB9 Owo+Pj4+Cj4+Pj4gZGlmZiAtLWdpdCBhL2FyY2gvcmlzY3Yva3ZtL3ZjcHVfb25lcmVnLmMgYi9h cmNoL3Jpc2N2L2t2bS92Y3B1X29uZXJlZy5jCj4+Pj4gaW5kZXggYjMxOWM0YzEzYzU0Li42Zjgz M2VjMjM0NGEgMTAwNjQ0Cj4+Pj4gLS0tIGEvYXJjaC9yaXNjdi9rdm0vdmNwdV9vbmVyZWcuYwo+ Pj4+ICsrKyBiL2FyY2gvcmlzY3Yva3ZtL3ZjcHVfb25lcmVnLmMKPj4+PiBAQCAtMzQsOSArMzQs MTEgQEAgc3RhdGljIGNvbnN0IHVuc2lnbmVkIGxvbmcga3ZtX2lzYV9leHRfYXJyW10gPSB7Cj4+ Pj4gICAgICAgICBbS1ZNX1JJU0NWX0lTQV9FWFRfTV0gPSBSSVNDVl9JU0FfRVhUX20sCj4+Pj4g ICAgICAgICBbS1ZNX1JJU0NWX0lTQV9FWFRfVl0gPSBSSVNDVl9JU0FfRVhUX3YsCj4+Pj4gICAg ICAgICAvKiBNdWx0aSBsZXR0ZXIgZXh0ZW5zaW9ucyAoYWxwaGFiZXRpY2FsbHkgc29ydGVkKSAq Lwo+Pj4+ICsgICAgICAgW0tWTV9SSVNDVl9JU0FfRVhUX1NNTlBNXSA9IFJJU0NWX0lTQV9FWFRf U1NOUE0sCj4+Pgo+Pj4gV2h5IG5vdCB1c2UgS1ZNX0lTQV9FWFRfQVJSKCkgbWFjcm8gaGVyZSA/ Cj4+Cj4+IEJlY2F1c2UgdGhlIGV4dGVuc2lvbiBuYW1lIGluIHRoZSBob3N0IGRvZXMgbm90IG1h dGNoIHRoZSBleHRlbnNpb24gbmFtZSBpbiB0aGUKPj4gZ3Vlc3QuIFBvaW50ZXIgbWFza2luZyBm b3IgSFMgbW9kZSBpcyBwcm92aWRlZCBieSBTbW5wbS4gUG9pbnRlciBtYXNraW5nIGZvciBWUwo+ PiBtb2RlIGlzIHByb3ZpZGVkIGJ5IFNzbnBtIGF0IHRoZSBoYXJkd2FyZSBsZXZlbCwgYnV0IHRo aXMgbmVlZHMgdG8gYXBwZWFyIHRvIHRoZQo+PiBndWVzdCBhcyBpZiBTbW5wbSB3YXMgaW1wbGVt ZW50ZWQsIHNpbmNlIHRoZSBndWVzdCB0aGlua3MgaXQgaXMgcnVubmluZyBvbiBiYXJlCj4+IG1l dGFsLgo+IAo+IE9rYXksIG1ha2VzIHNlbnNlLgo+IAo+Pgo+Pj4+ICAgICAgICAgS1ZNX0lTQV9F WFRfQVJSKFNNU1RBVEVFTiksCj4+Pj4gICAgICAgICBLVk1fSVNBX0VYVF9BUlIoU1NBSUEpLAo+ Pj4+ICAgICAgICAgS1ZNX0lTQV9FWFRfQVJSKFNTQ09GUE1GKSwKPj4+PiArICAgICAgIEtWTV9J U0FfRVhUX0FSUihTU05QTSksCj4+Pj4gICAgICAgICBLVk1fSVNBX0VYVF9BUlIoU1NUQyksCj4+ Pj4gICAgICAgICBLVk1fSVNBX0VYVF9BUlIoU1ZJTlZBTCksCj4+Pj4gICAgICAgICBLVk1fSVNB X0VYVF9BUlIoU1ZOQVBPVCksCj4+Pj4gQEAgLTEyOSw2ICsxMzEsNyBAQCBzdGF0aWMgYm9vbCBr dm1fcmlzY3ZfdmNwdV9pc2FfZGlzYWJsZV9hbGxvd2VkKHVuc2lnbmVkIGxvbmcgZXh0KQo+Pj4+ ICAgICAgICAgY2FzZSBLVk1fUklTQ1ZfSVNBX0VYVF9NOgo+Pj4+ICAgICAgICAgLyogVGhlcmUg aXMgbm90IGFyY2hpdGVjdHVyYWwgY29uZmlnIGJpdCB0byBkaXNhYmxlIHNzY29mcG1mIGNvbXBs ZXRlbHkgKi8KPj4+PiAgICAgICAgIGNhc2UgS1ZNX1JJU0NWX0lTQV9FWFRfU1NDT0ZQTUY6Cj4+ Pj4gKyAgICAgICBjYXNlIEtWTV9SSVNDVl9JU0FfRVhUX1NTTlBNOgo+Pj4KPj4+IFdoeSBub3Qg YWRkIEtWTV9SSVNDVl9JU0FfRVhUX1NNTlBNIGhlcmUgPwo+Pj4KPj4+IERpc2FibGluZyBTbW5w bSBmcm9tIEtWTSB1c2VyIHNwYWNlIGlzIHZlcnkgZGlmZmVyZW50IGZyb20KPj4+IGRpc2FibGlu ZyBTbW5wbSBmcm9tIEd1ZXN0IHVzaW5nIFNCSSBGV0ZUIGV4dGVuc2lvbi4KPj4KPj4gVW50aWwg YSBzdWNjZXNzZnVsIFNCSSBGV0ZUIGNhbGwgdG8gS1ZNIHRvIGVuYWJsZSBwb2ludGVyIG1hc2tp bmcgZm9yIFZTIG1vZGUsCj4+IHRoZSBleGlzdGVuY2Ugb2YgU21ucG0gaGFzIG5vIHZpc2libGUg ZWZmZWN0IG9uIHRoZSBndWVzdC4gU28gZmFpbGluZyB0aGUgU0JJCj4+IGNhbGwgaXMgc3VmZmlj aWVudCB0byBwcmV0ZW5kIHRoYXQgdGhlIGhhcmR3YXJlIGRvZXMgbm90IHN1cHBvcnQgU21ucG0u Cj4+Cj4+PiBUaGUgS1ZNIHVzZXIgc3BhY2Ugc2hvdWxkIGFsd2F5cyBhZGQgU21ucG0gaW4gdGhl Cj4+PiBHdWVzdCBJU0Egc3RyaW5nIHdoZW5ldmVyIHRoZSBIb3N0IElTQSBzdHJpbmcgaGFzIGl0 Lgo+Pgo+PiBJIGRpc2FncmVlLiBBbGxvd2luZyB1c2Vyc3BhY2UgdG8gZGlzYWJsZSBleHRlbnNp b25zIGlzIHVzZWZ1bCBmb3IgdGVzdGluZyBhbmQKPj4gdG8gc3VwcG9ydCBtaWdyYXRpb24gdG8g aG9zdHMgd2hpY2ggZG8gbm90IHN1cHBvcnQgdGhvc2UgZXh0ZW5zaW9ucy4gU28gSSB3b3VsZAo+ PiBvbmx5IGFkZCBleHRlbnNpb25zIHRvIHRoaXMgbGlzdCBpZiB0aGVyZSBpcyBubyBwb3NzaWJs ZSB3YXkgdG8gZGlzYWJsZSB0aGVtLgo+IAo+IEkgYW0gbm90IHNheWluZyB0byBkaXNhbGxvdyBL Vk0gdXNlciBzcGFjZSBkaXNhYmxpbmcgU21ucG0uCgpUaGVuIEknbSBjb25mdXNlZC4gVGhpcyBp cyB0aGUgInJldHVybiBmYWxzZTsiIHN3aXRjaCBjYXNlIGluc2lkZQprdm1fcmlzY3ZfdmNwdV9p c2FfZGlzYWJsZV9hbGxvd2VkKCkuIElmIEkgYWRkIEtWTV9SSVNDVl9JU0FfRVhUX1NNTlBNIGhl cmUsCnRoZW4gKHVubGVzcyBJIGFtIG1pc3JlYWRpbmcgdGhlIGNvZGUpIEkgYW0gZGlzYWxsb3dp bmcgS1ZNIHVzZXJzcGFjZSBmcm9tCmRpc2FibGluZyBTbW5wbSBpbiB0aGUgZ3Vlc3QgKGkuZS4g cHJldmVudGluZyBLVk0gdXNlcnNwYWNlIGZyb20gcmVtb3ZpbmcgU21ucG0KZnJvbSB0aGUgZ3Vl c3QgSVNBIHN0cmluZykuIElmIHRoYXQgaXMgbm90IGRlc2lyZWQsIHRoZW4gd2h5IGRvIHlvdSBz dWdnZXN0IEkKYWRkIEtWTV9SSVNDVl9JU0FfRVhUX1NNTlBNIGhlcmU/Cgo+IFRoZSBwcmVzZW5j ZSBvZiBTbW5wbSBpbiBJU0Egb25seSBtZWFucyB0aGF0IGl0IGlzIHByZXNlbnQgaW4gSFcKPiBi dXQgaXQgbmVlZHMgdG8gYmUgZXhwbGljaXRseSBjb25maWd1cmVkL2VuYWJsZWQgdXNpbmcgU0JJ IEZXRlQuCj4gCj4gS1ZNIHVzZXIgc3BhY2UgY2FuIGNlcnRhaW5seSBkaXNhYmxlIGV4dGVuc2lv bnMgYnkgbm90IGFkZGluZyBpdCB0bwo+IElTQSBzdHJpbmcgYmFzZWQgb24gdGhlIEtWTVRPT0wv UUVNVS1LVk0gY29tbWFuZCBsaW5lIG9wdGlvbi4KPiBBZGRpdGlvbmFsbHksIHdoZW4gU0JJIEZX RlQgaXMgYWRkZWQgdG8gS1ZNIFJJU0MtVi4gSXQgd2lsbCBoYXZlIGl0cwo+IG93biB3YXkgdG8g ZXhwbGljaXRseSBkaXNhYmxlIGZpcm13YXJlIGZlYXR1cmVzIGZyb20gS1ZNIHVzZXIgc3BhY2Uu CgpJIHRoaW5rIHdlIGFncmVlIG9uIHRoaXMsIGJ1dCB5b3VyIGV4cGxhbmF0aW9uIGhlcmUgYXBw ZWFycyB0byBjb25mbGljdCB3aXRoCnlvdXIgc3VnZ2VzdGVkIGNvZGUgY2hhbmdlLiBBcG9sb2dp ZXMgaWYgSSdtIG1pc3Npbmcgc29tZXRoaW5nLgoKUmVnYXJkcywKU2FtdWVsCgo+Pj4gVGhlIEd1 ZXN0IG11c3QgZXhwbGljaXRseSB1c2UgU0JJIEZXRlQgdG8gZW5hYmxlCj4+PiBTbW5wbSBvbmx5 IGFmdGVyIGl0IHNlZXMgU21ucG0gaW4gSVNBIHN0cmluZy4KPj4KPj4gWWVzLCBleGFjdGx5LCBh bmQgdGhlIHB1cnBvc2Ugb2Ygbm90IGluY2x1ZGluZyBTbW5wbSBpbiB0aGUgc3dpdGNoIGNhc2Ug aGVyZSBpcwo+PiBzbyB0aGF0IEtWTSB1c2VyIHNwYWNlIGNhbiBjb250cm9sIHdoZXRoZXIgb3Ig bm90IGl0IGFwcGVhcnMgaW4gdGhlIElTQSBzdHJpbmcuCj4+Cj4+IFJlZ2FyZHMsCj4+IFNhbXVl bAo+Pgo+Pj4+ICAgICAgICAgY2FzZSBLVk1fUklTQ1ZfSVNBX0VYVF9TU1RDOgo+Pj4+ICAgICAg ICAgY2FzZSBLVk1fUklTQ1ZfSVNBX0VYVF9TVklOVkFMOgo+Pj4+ICAgICAgICAgY2FzZSBLVk1f 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Subject: Re: [PATCH v4 09/10] RISC-V: KVM: Allow Smnpm and Ssnpm extensions for guests To: Anup Patel Cc: Anup Patel , Palmer Dabbelt , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Catalin Marinas , linux-kernel@vger.kernel.org, Conor Dooley , kasan-dev@googlegroups.com, Atish Patra , Evgenii Stepanov , Krzysztof Kozlowski , Rob Herring , "Kirill A . Shutemov" , kvm-riscv@lists.infradead.org References: <20240829010151.2813377-1-samuel.holland@sifive.com> <20240829010151.2813377-10-samuel.holland@sifive.com> From: Samuel Holland Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Anup, On 2024-09-04 9:45 AM, Anup Patel wrote: > On Wed, Sep 4, 2024 at 8:01 PM Samuel Holland wrote: >> On 2024-09-04 7:17 AM, Anup Patel wrote: >>> On Thu, Aug 29, 2024 at 6:32 AM Samuel Holland >>> wrote: >>>> >>>> The interface for controlling pointer masking in VS-mode is henvcfg.PMM, >>>> which is part of the Ssnpm extension, even though pointer masking in >>>> HS-mode is provided by the Smnpm extension. As a result, emulating Smnpm >>>> in the guest requires (only) Ssnpm on the host. >>>> >>>> Since the guest configures Smnpm through the SBI Firmware Features >>>> interface, the extension can be disabled by failing the SBI call. Ssnpm >>>> cannot be disabled without intercepting writes to the senvcfg CSR. >>>> >>>> Signed-off-by: Samuel Holland >>>> --- >>>> >>>> (no changes since v2) >>>> >>>> Changes in v2: >>>> - New patch for v2 >>>> >>>> arch/riscv/include/uapi/asm/kvm.h | 2 ++ >>>> arch/riscv/kvm/vcpu_onereg.c | 3 +++ >>>> 2 files changed, 5 insertions(+) >>>> >>>> diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h >>>> index e97db3296456..4f24201376b1 100644 >>>> --- a/arch/riscv/include/uapi/asm/kvm.h >>>> +++ b/arch/riscv/include/uapi/asm/kvm.h >>>> @@ -175,6 +175,8 @@ enum KVM_RISCV_ISA_EXT_ID { >>>> KVM_RISCV_ISA_EXT_ZCF, >>>> KVM_RISCV_ISA_EXT_ZCMOP, >>>> KVM_RISCV_ISA_EXT_ZAWRS, >>>> + KVM_RISCV_ISA_EXT_SMNPM, >>>> + KVM_RISCV_ISA_EXT_SSNPM, >>>> KVM_RISCV_ISA_EXT_MAX, >>>> }; >>>> >>>> diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c >>>> index b319c4c13c54..6f833ec2344a 100644 >>>> --- a/arch/riscv/kvm/vcpu_onereg.c >>>> +++ b/arch/riscv/kvm/vcpu_onereg.c >>>> @@ -34,9 +34,11 @@ static const unsigned long kvm_isa_ext_arr[] = { >>>> [KVM_RISCV_ISA_EXT_M] = RISCV_ISA_EXT_m, >>>> [KVM_RISCV_ISA_EXT_V] = RISCV_ISA_EXT_v, >>>> /* Multi letter extensions (alphabetically sorted) */ >>>> + [KVM_RISCV_ISA_EXT_SMNPM] = RISCV_ISA_EXT_SSNPM, >>> >>> Why not use KVM_ISA_EXT_ARR() macro here ? >> >> Because the extension name in the host does not match the extension name in the >> guest. Pointer masking for HS mode is provided by Smnpm. Pointer masking for VS >> mode is provided by Ssnpm at the hardware level, but this needs to appear to the >> guest as if Smnpm was implemented, since the guest thinks it is running on bare >> metal. > > Okay, makes sense. > >> >>>> KVM_ISA_EXT_ARR(SMSTATEEN), >>>> KVM_ISA_EXT_ARR(SSAIA), >>>> KVM_ISA_EXT_ARR(SSCOFPMF), >>>> + KVM_ISA_EXT_ARR(SSNPM), >>>> KVM_ISA_EXT_ARR(SSTC), >>>> KVM_ISA_EXT_ARR(SVINVAL), >>>> KVM_ISA_EXT_ARR(SVNAPOT), >>>> @@ -129,6 +131,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) >>>> case KVM_RISCV_ISA_EXT_M: >>>> /* There is not architectural config bit to disable sscofpmf completely */ >>>> case KVM_RISCV_ISA_EXT_SSCOFPMF: >>>> + case KVM_RISCV_ISA_EXT_SSNPM: >>> >>> Why not add KVM_RISCV_ISA_EXT_SMNPM here ? >>> >>> Disabling Smnpm from KVM user space is very different from >>> disabling Smnpm from Guest using SBI FWFT extension. >> >> Until a successful SBI FWFT call to KVM to enable pointer masking for VS mode, >> the existence of Smnpm has no visible effect on the guest. So failing the SBI >> call is sufficient to pretend that the hardware does not support Smnpm. >> >>> The KVM user space should always add Smnpm in the >>> Guest ISA string whenever the Host ISA string has it. >> >> I disagree. Allowing userspace to disable extensions is useful for testing and >> to support migration to hosts which do not support those extensions. So I would >> only add extensions to this list if there is no possible way to disable them. > > I am not saying to disallow KVM user space disabling Smnpm. Then I'm confused. This is the "return false;" switch case inside kvm_riscv_vcpu_isa_disable_allowed(). If I add KVM_RISCV_ISA_EXT_SMNPM here, then (unless I am misreading the code) I am disallowing KVM userspace from disabling Smnpm in the guest (i.e. preventing KVM userspace from removing Smnpm from the guest ISA string). If that is not desired, then why do you suggest I add KVM_RISCV_ISA_EXT_SMNPM here? > The presence of Smnpm in ISA only means that it is present in HW > but it needs to be explicitly configured/enabled using SBI FWFT. > > KVM user space can certainly disable extensions by not adding it to > ISA string based on the KVMTOOL/QEMU-KVM command line option. > Additionally, when SBI FWFT is added to KVM RISC-V. It will have its > own way to explicitly disable firmware features from KVM user space. I think we agree on this, but your explanation here appears to conflict with your suggested code change. Apologies if I'm missing something. Regards, Samuel >>> The Guest must explicitly use SBI FWFT to enable >>> Smnpm only after it sees Smnpm in ISA string. >> >> Yes, exactly, and the purpose of not including Smnpm in the switch case here is >> so that KVM user space can control whether or not it appears in the ISA string. >> >> Regards, >> Samuel >> >>>> case KVM_RISCV_ISA_EXT_SSTC: >>>> case KVM_RISCV_ISA_EXT_SVINVAL: >>>> case KVM_RISCV_ISA_EXT_SVNAPOT: >>>> -- >>>> 2.45.1 >>>> >>>> >>>> _______________________________________________ >>>> linux-riscv mailing list >>>> linux-riscv@lists.infradead.org >>>> http://lists.infradead.org/mailman/listinfo/linux-riscv >>> >>> Regards, >>> Anup >> > > Regards, > Anup