diff for duplicates of <2115968.yvb8ppzjmL@phil> diff --git a/a/1.txt b/N1/1.txt index 0524b5b..6be82c3 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -21,15 +21,13 @@ The following changes since commit 29b4817d4018df78086157ea3a55c1d9424a7cfc: are available in the git repository at: - git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git ta= -gs/v4.9-rockchip-clk1 + git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/v4.9-rockchip-clk1 for you to fetch changes up to 7b0f9e357ac838f640b10fb3db1ac35d9a5fa8de: - clk: rockchip: use the dclk_vop_frac clock ids on rk3399 (2016-09-04 23:4= -8:19 +0200) + clk: rockchip: use the dclk_vop_frac clock ids on rk3399 (2016-09-04 23:48:19 +0200) -=2D--------------------------------------------------------------- +---------------------------------------------------------------- The biggest addition is probably the special clock-type for ddr clock control. While reading that clock is done the normal way from the registers, setting it always requires some sort of special handling @@ -53,7 +51,7 @@ And interestingly an iomap fix for the legacy gate driver, where I hopefully could deter the submitter from actually using that in any new works. -=2D--------------------------------------------------------------- +---------------------------------------------------------------- Arvind Yadav (1): clk: rockchip: handle of_iomap failures in legacy clock driver @@ -61,8 +59,7 @@ Chris Zhong (1): clk: rockchip: mark rk3399 hdcp_noc and vio_noc as critical Douglas Anderson (1): - clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional divide= -rs + clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividers Elaine Zhang (1): clk: rockchip: delete the CLK_IGNORE_UNUSED from aclk_pcie on rk3399 @@ -71,7 +68,7 @@ Heiko Stuebner (2): Merge branch 'v4.9-shared/sip-hdr' into v4.9-clk/next Merge branch 'v4.9-shared/clkids' into v4.9-clk/next -Heiko St=FCbner (1): +Heiko Stübner (1): clk: rockchip: use general clock flag when registering pll Lin Huang (4): @@ -84,16 +81,14 @@ Shunqian Zheng (1): clk: rockchip: add 2016M to big cpu clk rate table on rk3399 Xing Zheng (1): - clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for H= -DMI + clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMI Yakir Yang (2): clk: rockchip: add dclk_vop_frac ids for rk3399 vop clk: rockchip: use the dclk_vop_frac clock ids on rk3399 drivers/clk/rockchip/Makefile | 1 + - drivers/clk/rockchip/clk-ddr.c | 154 +++++++++++++++++++++++++++++= -++++ + drivers/clk/rockchip/clk-ddr.c | 154 +++++++++++++++++++++++++++++++++ drivers/clk/rockchip/clk-pll.c | 4 +- drivers/clk/rockchip/clk-rk3399.c | 56 ++++++++---- drivers/clk/rockchip/clk-rockchip.c | 7 +- diff --git a/a/content_digest b/N1/content_digest index c9a87db..60d47e3 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -30,15 +30,13 @@ "\n" "are available in the git repository at:\n" "\n" - " git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git ta=\n" - "gs/v4.9-rockchip-clk1\n" + " git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/v4.9-rockchip-clk1\n" "\n" "for you to fetch changes up to 7b0f9e357ac838f640b10fb3db1ac35d9a5fa8de:\n" "\n" - " clk: rockchip: use the dclk_vop_frac clock ids on rk3399 (2016-09-04 23:4=\n" - "8:19 +0200)\n" + " clk: rockchip: use the dclk_vop_frac clock ids on rk3399 (2016-09-04 23:48:19 +0200)\n" "\n" - "=2D---------------------------------------------------------------\n" + "----------------------------------------------------------------\n" "The biggest addition is probably the special clock-type for ddr clock\n" "control. While reading that clock is done the normal way from the\n" "registers, setting it always requires some sort of special handling\n" @@ -62,7 +60,7 @@ "hopefully could deter the submitter from actually using that in any\n" "new works.\n" "\n" - "=2D---------------------------------------------------------------\n" + "----------------------------------------------------------------\n" "Arvind Yadav (1):\n" " clk: rockchip: handle of_iomap failures in legacy clock driver\n" "\n" @@ -70,8 +68,7 @@ " clk: rockchip: mark rk3399 hdcp_noc and vio_noc as critical\n" "\n" "Douglas Anderson (1):\n" - " clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional divide=\n" - "rs\n" + " clk: rockchip: drop CLK_SET_RATE_PARENT from rk3399 fractional dividers\n" "\n" "Elaine Zhang (1):\n" " clk: rockchip: delete the CLK_IGNORE_UNUSED from aclk_pcie on rk3399\n" @@ -80,7 +77,7 @@ " Merge branch 'v4.9-shared/sip-hdr' into v4.9-clk/next\n" " Merge branch 'v4.9-shared/clkids' into v4.9-clk/next\n" "\n" - "Heiko St=FCbner (1):\n" + "Heiko St\303\274bner (1):\n" " clk: rockchip: use general clock flag when registering pll\n" "\n" "Lin Huang (4):\n" @@ -93,16 +90,14 @@ " clk: rockchip: add 2016M to big cpu clk rate table on rk3399\n" "\n" "Xing Zheng (1):\n" - " clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for H=\n" - "DMI\n" + " clk: rockchip: add 65MHz and 106.5MHz rates to rk3399 plls used for HDMI\n" "\n" "Yakir Yang (2):\n" " clk: rockchip: add dclk_vop_frac ids for rk3399 vop\n" " clk: rockchip: use the dclk_vop_frac clock ids on rk3399\n" "\n" " drivers/clk/rockchip/Makefile | 1 +\n" - " drivers/clk/rockchip/clk-ddr.c | 154 +++++++++++++++++++++++++++++=\n" - "++++\n" + " drivers/clk/rockchip/clk-ddr.c | 154 +++++++++++++++++++++++++++++++++\n" " drivers/clk/rockchip/clk-pll.c | 4 +-\n" " drivers/clk/rockchip/clk-rk3399.c | 56 ++++++++----\n" " drivers/clk/rockchip/clk-rockchip.c | 7 +-\n" @@ -114,4 +109,4 @@ " create mode 100644 drivers/clk/rockchip/clk-ddr.c\n" create mode 100644 include/soc/rockchip/rockchip_sip.h -94966c32ccc96e9634b6641b4b8056728bae1780cee19361c1ab8ea720a3d134 +998bb2f3852c84eab17fa30f5d8a3c7e082354078bad6cff1bf74ab71d0c7f4f
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.