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From: Andrew Cooper <andrew.cooper3@citrix.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "Wei Liu" <wl@xen.org>, "Roger Pau Monné" <roger.pau@citrix.com>,
	"Simone Ballarin" <simone.ballarin@bugseng.com>,
	"Gianluca Luparini" <gianluca.luparini@bugseng.com>,
	"Stefano Stabellini" <sstabellini@kernel.org>,
	"xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>
Subject: Re: [PATCH] x86: drop old (32-bit-only) MSR definitions
Date: Mon, 17 Jul 2023 13:23:13 +0100	[thread overview]
Message-ID: <214bdf26-9f30-7ee2-e59f-e8f0c96937ee@citrix.com> (raw)
In-Reply-To: <ee342a26-5f26-0e47-06a6-c74fdb3270d6@suse.com>

On 17/07/2023 12:52 pm, Jan Beulich wrote:
> On 17.07.2023 12:33, Andrew Cooper wrote:
>> On 17/07/2023 10:17 am, Jan Beulich wrote:
>>>  /* Intel defined MSRs. */
>>> -#define MSR_IA32_P5_MC_ADDR		0x00000000
>>> -#define MSR_IA32_P5_MC_TYPE		0x00000001
>> These are architectural.  They still exist in all Intel and AMD CPUs.
>>
>> I'd suggest keeping them, because I think we're required to expose them
>> when advertising MCA.
> We have them twice, and I've kept the instances without IA32 in their names
> (at the very top of the file, i.e. already in the "new style" section).

Ah ok.

Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>


      reply	other threads:[~2023-07-17 12:24 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-17  9:17 [PATCH] x86: drop old (32-bit-only) MSR definitions Jan Beulich
2023-07-17 10:33 ` Andrew Cooper
2023-07-17 11:52   ` Jan Beulich
2023-07-17 12:23     ` Andrew Cooper [this message]

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