From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from perceval.ideasonboard.com ([213.167.242.64]:38160 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727783AbeLFJu0 (ORCPT ); Thu, 6 Dec 2018 04:50:26 -0500 From: Laurent Pinchart To: Kuninori Morimoto Cc: Laurent Pinchart , "dri-devel@lists.freedesktop.org" , "linux-renesas-soc@vger.kernel.org" , Ulrich Hecht , Kieran Bingham , KOJI MATSUOKA Subject: Re: [PATCH v2 07/16] drm: rcar-du: Use LVDS PLL clock as dot clock when possible Date: Thu, 06 Dec 2018 11:50:59 +0200 Message-ID: <2156355.nrP3YJkyIb@avalon> In-Reply-To: <87pnur1ho1.wl-kuninori.morimoto.gx@renesas.com> References: <20180914091046.483-1-laurent.pinchart+renesas@ideasonboard.com> <20180914091046.483-8-laurent.pinchart+renesas@ideasonboard.com> <87pnur1ho1.wl-kuninori.morimoto.gx@renesas.com> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: Hi Morimoto-san, On Tuesday, 27 November 2018 02:44:58 EET Kuninori Morimoto wrote: > Hi Laurent > > Sorry for super late response. > I got opinion from BSP team about this patch. No worries. My reply is late too I'm afraid :-S > > On selected SoCs, the DU can use the clock output by the LVDS encoder > > PLL as its input dot clock. This feature is optional, but on the D3 and > > E3 SoC it is often the only way to obtain a precise dot clock frequency, > > as the other available clocks (CPG-generated clock and external clock) > > usually have fixed rates. > > > > Add a DU model information field to describe which DU channels can use > > the LVDS PLL output clock as their input clock, and configure clock > > routing accordingly. > > > > This feature is available on H2, M2-W, M2-N, D3 and E3 SoCs, with D3 and > > E3 being the primary targets. It is left disabled in this commit, and > > will be enabled per-SoC after careful testing. > > > > At the hardware level, clock routing is configured at runtime in two > > steps, first selecting an internal dot clock between the LVDS PLL clock > > and the external DOTCLKIN clock, and then selecting between the internal > > dot clock and the CPG-generated clock. The first part requires stopping > > the whole DU group in order for the change to take effect, thus causing > > flickering on the screen. For this reason we currently hardcode the > > clock source to the LVDS PLL clock if available, and allow flicker-free > > selection of the external DOTCLKIN clock or CPG-generated clock > > otherwise. A more dynamic clock selection process can be implemented > > later if the need arises. > > > > Signed-off-by: Laurent Pinchart > > > > Tested-by: Jacopo Mondi > > --- > > (snip) > > > + didsr = DIDSR_CODE; > > + for (i = 0; i < num_crtcs; ++i, ++rcrtc) { > > + if (rcdu->info->lvds_clk_mask & BIT(rcrtc->index)) > > + didsr |= DIDSR_LCDS_LVDS0(i) > > + | DIDSR_PDCS_CLK(i, 0); > > + else > > + didsr |= DIDSR_LCDS_DCLKIN(i) > > + | DIDSR_PDCS_CLK(i, 0); > > + } > > Here, this is for DU pin settings, and fixed for > > DU_DOTCLKIN0 -> DU0 > DU_DOTCLKIN1 -> DU1 > > But on E3 (Ebisu) board, it has only DU_DOTCLKIN0. > We might use like this > > DU_DOTCLKIN0 -> DU0 > DU_DOTCLKIN0 -> DU1 > > It is possible to adjust to this situation ? > DIDSR :: PDCSn allows only 0 I think this would make sense. I'm not sure how to implement that, but I'll give it a try. What is the priority ? -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [PATCH v2 07/16] drm: rcar-du: Use LVDS PLL clock as dot clock when possible Date: Thu, 06 Dec 2018 11:50:59 +0200 Message-ID: <2156355.nrP3YJkyIb@avalon> References: <20180914091046.483-1-laurent.pinchart+renesas@ideasonboard.com> <20180914091046.483-8-laurent.pinchart+renesas@ideasonboard.com> <87pnur1ho1.wl-kuninori.morimoto.gx@renesas.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by gabe.freedesktop.org (Postfix) with ESMTPS id C3EF96E55A for ; Thu, 6 Dec 2018 09:50:26 +0000 (UTC) In-Reply-To: <87pnur1ho1.wl-kuninori.morimoto.gx@renesas.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Kuninori Morimoto Cc: Ulrich Hecht , Laurent Pinchart , Kieran Bingham , "dri-devel@lists.freedesktop.org" , KOJI MATSUOKA , "linux-renesas-soc@vger.kernel.org" List-Id: dri-devel@lists.freedesktop.org SGkgTW9yaW1vdG8tc2FuLAoKT24gVHVlc2RheSwgMjcgTm92ZW1iZXIgMjAxOCAwMjo0NDo1OCBF RVQgS3VuaW5vcmkgTW9yaW1vdG8gd3JvdGU6Cj4gSGkgTGF1cmVudAo+IAo+IFNvcnJ5IGZvciBz dXBlciBsYXRlIHJlc3BvbnNlLgo+IEkgZ290IG9waW5pb24gZnJvbSBCU1AgdGVhbSBhYm91dCB0 aGlzIHBhdGNoLgoKTm8gd29ycmllcy4gTXkgcmVwbHkgaXMgbGF0ZSB0b28gSSdtIGFmcmFpZCA6 LVMKCj4gPiBPbiBzZWxlY3RlZCBTb0NzLCB0aGUgRFUgY2FuIHVzZSB0aGUgY2xvY2sgb3V0cHV0 IGJ5IHRoZSBMVkRTIGVuY29kZXIKPiA+IFBMTCBhcyBpdHMgaW5wdXQgZG90IGNsb2NrLiBUaGlz IGZlYXR1cmUgaXMgb3B0aW9uYWwsIGJ1dCBvbiB0aGUgRDMgYW5kCj4gPiBFMyBTb0MgaXQgaXMg b2Z0ZW4gdGhlIG9ubHkgd2F5IHRvIG9idGFpbiBhIHByZWNpc2UgZG90IGNsb2NrIGZyZXF1ZW5j eSwKPiA+IGFzIHRoZSBvdGhlciBhdmFpbGFibGUgY2xvY2tzIChDUEctZ2VuZXJhdGVkIGNsb2Nr IGFuZCBleHRlcm5hbCBjbG9jaykKPiA+IHVzdWFsbHkgaGF2ZSBmaXhlZCByYXRlcy4KPiA+IAo+ ID4gQWRkIGEgRFUgbW9kZWwgaW5mb3JtYXRpb24gZmllbGQgdG8gZGVzY3JpYmUgd2hpY2ggRFUg Y2hhbm5lbHMgY2FuIHVzZQo+ID4gdGhlIExWRFMgUExMIG91dHB1dCBjbG9jayBhcyB0aGVpciBp bnB1dCBjbG9jaywgYW5kIGNvbmZpZ3VyZSBjbG9jawo+ID4gcm91dGluZyBhY2NvcmRpbmdseS4K PiA+IAo+ID4gVGhpcyBmZWF0dXJlIGlzIGF2YWlsYWJsZSBvbiBIMiwgTTItVywgTTItTiwgRDMg YW5kIEUzIFNvQ3MsIHdpdGggRDMgYW5kCj4gPiBFMyBiZWluZyB0aGUgcHJpbWFyeSB0YXJnZXRz LiBJdCBpcyBsZWZ0IGRpc2FibGVkIGluIHRoaXMgY29tbWl0LCBhbmQKPiA+IHdpbGwgYmUgZW5h YmxlZCBwZXItU29DIGFmdGVyIGNhcmVmdWwgdGVzdGluZy4KPiA+IAo+ID4gQXQgdGhlIGhhcmR3 YXJlIGxldmVsLCBjbG9jayByb3V0aW5nIGlzIGNvbmZpZ3VyZWQgYXQgcnVudGltZSBpbiB0d28K PiA+IHN0ZXBzLCBmaXJzdCBzZWxlY3RpbmcgYW4gaW50ZXJuYWwgZG90IGNsb2NrIGJldHdlZW4g dGhlIExWRFMgUExMIGNsb2NrCj4gPiBhbmQgdGhlIGV4dGVybmFsIERPVENMS0lOIGNsb2NrLCBh bmQgdGhlbiBzZWxlY3RpbmcgYmV0d2VlbiB0aGUgaW50ZXJuYWwKPiA+IGRvdCBjbG9jayBhbmQg dGhlIENQRy1nZW5lcmF0ZWQgY2xvY2suIFRoZSBmaXJzdCBwYXJ0IHJlcXVpcmVzIHN0b3BwaW5n Cj4gPiB0aGUgd2hvbGUgRFUgZ3JvdXAgaW4gb3JkZXIgZm9yIHRoZSBjaGFuZ2UgdG8gdGFrZSBl ZmZlY3QsIHRodXMgY2F1c2luZwo+ID4gZmxpY2tlcmluZyBvbiB0aGUgc2NyZWVuLiBGb3IgdGhp cyByZWFzb24gd2UgY3VycmVudGx5IGhhcmRjb2RlIHRoZQo+ID4gY2xvY2sgc291cmNlIHRvIHRo ZSBMVkRTIFBMTCBjbG9jayBpZiBhdmFpbGFibGUsIGFuZCBhbGxvdyBmbGlja2VyLWZyZWUKPiA+ IHNlbGVjdGlvbiBvZiB0aGUgZXh0ZXJuYWwgRE9UQ0xLSU4gY2xvY2sgb3IgQ1BHLWdlbmVyYXRl ZCBjbG9jawo+ID4gb3RoZXJ3aXNlLiBBIG1vcmUgZHluYW1pYyBjbG9jayBzZWxlY3Rpb24gcHJv Y2VzcyBjYW4gYmUgaW1wbGVtZW50ZWQKPiA+IGxhdGVyIGlmIHRoZSBuZWVkIGFyaXNlcy4KPiA+ IAo+ID4gU2lnbmVkLW9mZi1ieTogTGF1cmVudCBQaW5jaGFydAo+ID4gPGxhdXJlbnQucGluY2hh cnQrcmVuZXNhc0BpZGVhc29uYm9hcmQuY29tPgo+ID4gVGVzdGVkLWJ5OiBKYWNvcG8gTW9uZGkg PGphY29wbytyZW5lc2FzQGptb25kaS5vcmc+Cj4gPiAtLS0KPiAKPiAoc25pcCkKPiAKPiA+ICsJ ZGlkc3IgPSBESURTUl9DT0RFOwo+ID4gKwlmb3IgKGkgPSAwOyBpIDwgbnVtX2NydGNzOyArK2ks ICsrcmNydGMpIHsKPiA+ICsJCWlmIChyY2R1LT5pbmZvLT5sdmRzX2Nsa19tYXNrICYgQklUKHJj cnRjLT5pbmRleCkpCj4gPiArCQkJZGlkc3IgfD0gRElEU1JfTENEU19MVkRTMChpKQo+ID4gKwkJ CSAgICAgIHwgIERJRFNSX1BEQ1NfQ0xLKGksIDApOwo+ID4gKwkJZWxzZQo+ID4gKwkJCWRpZHNy IHw9IERJRFNSX0xDRFNfRENMS0lOKGkpCj4gPiArCQkJICAgICAgfCAgRElEU1JfUERDU19DTEso aSwgMCk7Cj4gPiArCX0KPiAKPiBIZXJlLCB0aGlzIGlzIGZvciBEVSBwaW4gc2V0dGluZ3MsIGFu ZCBmaXhlZCBmb3IKPiAKPiAJRFVfRE9UQ0xLSU4wIC0+IERVMAo+IAlEVV9ET1RDTEtJTjEgLT4g RFUxCj4gCj4gQnV0IG9uIEUzIChFYmlzdSkgYm9hcmQsIGl0IGhhcyBvbmx5IERVX0RPVENMS0lO MC4KPiBXZSBtaWdodCB1c2UgbGlrZSB0aGlzCj4gCj4gCURVX0RPVENMS0lOMCAtPiBEVTAKPiAJ RFVfRE9UQ0xLSU4wIC0+IERVMQo+IAo+IEl0IGlzIHBvc3NpYmxlIHRvIGFkanVzdCB0byB0aGlz IHNpdHVhdGlvbiA/Cj4gRElEU1IgOjogUERDU24gYWxsb3dzIG9ubHkgMAoKSSB0aGluayB0aGlz IHdvdWxkIG1ha2Ugc2Vuc2UuIEknbSBub3Qgc3VyZSBob3cgdG8gaW1wbGVtZW50IHRoYXQsIGJ1 dCBJJ2xsIApnaXZlIGl0IGEgdHJ5LiBXaGF0IGlzIHRoZSBwcmlvcml0eSA/CgotLSAKUmVnYXJk cywKCkxhdXJlbnQgUGluY2hhcnQKCgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX18KZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJl ZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGlu Zm8vZHJpLWRldmVsCg==