From: Tim Sander <tim@krieglstein.org>
To: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] State of ARM FIQ in Qemu
Date: Mon, 03 Nov 2014 17:22:27 +0100 [thread overview]
Message-ID: <2195206.F4HeItVKYs@dabox> (raw)
In-Reply-To: <CAOgzsHW4PVGik+-=Cc-YE=dHa92ZrKYwNfMWXRWzOME6MAxZVw@mail.gmail.com>
Hi Greg
Thanks for your fast reply.
> I am still in the process of getting the security extension portion of the
> GIC patches fully up and running. By the sounds of your use, it sounds
> like you just want FIQ support not necessarily secure GIC support. Would
> this be correct?
Yes. More elaborate i am working on a modified cortexa9 versatile express,
where i added my virtual test hardware.
> I recently sent out an updated set of patches for review that contain GIC
> interrupt grouping and FIQ enablement along with secure extension
> infrastructure. If interested, you can find the patches here:
>
> http://lists.nongnu.org/archive/html/qemu-devel/2014-10/msg03921.html
>
> Alternatively, it sounds like you have access to the Linaro GIT repos, in
> which case you can use the following repo/branch that contains the same
> patches. It is based on fairly recent upstream bits.
>
> repo: git://git.linaro.org/people/greg.bellows/qemu.git
> branch: tzqemu_gic_v2
>
> If you don't need the security extensions, then you shouldn't need to do
> anything to the code to get FIQ support on vexpress-a9/15 or virt machines.
Ok but i think i see a RAZ codepath in qemu when accessing the gic registers
configuring the interrupt group.
> Please let me know if you have any further questions or issues.
I have the problem that the secure_extn property is not set and i have not
figured out a way to set these. The corresponding code is a slighly modified
vexpress_common_init in hw/arm/vexpress.c.:519.
I guess setting the property would be done by
qdev_prop_set_bool(dev,"security_extn",TRUE);
but i fail to find the "dev" from the GIC i could use as argument.
Attached is also a snipped from a debugger run verifing that its indeed
s->security-extn which is missing.
Best regards
Tim
Breakpoint 3, gic_dist_writeb (opaque=0x555556368a80, offset=136, value=0) at
hw/intc/arm_gic.c:820
820 } else if (offset >= 0x80) {
(gdb) list
815 s->enabled = (value & 0x1);
816 DPRINTF("Distribution %sabled\n", s->enabled ? "En" :
"Dis");
817 }
818 } else if (offset < 4) {
819 /* ignored. */
820 } else if (offset >= 0x80) {
821 /* Interrupt Group Registers
822 *
823 * For GIC with Security Extn and Non-secure access RAZ/WI
824 * For GICv1 without Security Extn RAZ/WI
(gdb) n
826 if (!(s->security_extn && ns_access()) &&
(gdb) n
828 || s->revision == 2)) {
(gdb) n
999 gic_update(s);
(gdb) print s->security_extn
$2 = false
next prev parent reply other threads:[~2014-11-03 16:22 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-11-03 15:10 [Qemu-devel] State of ARM FIQ in Qemu Tim Sander
2014-11-03 15:33 ` Greg Bellows
2014-11-03 16:22 ` Tim Sander [this message]
2014-11-03 18:46 ` Greg Bellows
2014-11-04 15:40 ` Tim Sander
2014-11-04 18:33 ` Greg Bellows
2014-11-12 13:56 ` Tim Sander
2014-11-12 16:00 ` Greg Bellows
2014-11-13 13:58 ` Tim Sander
2014-11-13 15:09 ` Greg Bellows
2014-11-13 16:26 ` Tim Sander
2014-11-13 16:46 ` Peter Maydell
2014-11-13 20:09 ` Greg Bellows
2014-11-14 15:34 ` Tim Sander
2014-11-14 16:50 ` Greg Bellows
2014-11-17 14:33 ` Tim Sander
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