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Wed, 02 Sep 2026 23:06:47 -0700 (PDT) Received: from [192.168.0.22] ([211.226.54.223]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-39b08cacba5sm3183530a91.12.2026.09.02.23.06.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 02 Sep 2026 23:06:47 -0700 (PDT) Message-ID: <21bbbab6-192b-4243-980e-4167b450c478@gmail.com> Date: Thu, 3 Sep 2026 15:06:42 +0900 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3] hw/ufs: Reset controller and MCQ state on HCE transition to 0 Content-Language: ko To: Stanley Jhu , Jeuk Kim Cc: qemu-devel@nongnu.org, Jinyoung Choi References: <20260902081610.2290123-1-stanleyjhu@google.com> From: Jeuk Kim In-Reply-To: <20260902081610.2290123-1-stanleyjhu@google.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=jeuk20.kim@gmail.com; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: qemu development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 9/2/2026 5:16 PM, Stanley Jhu wrote: > According to the JEDEC Universal Flash Storage Host Controller Interface > (UFSHCI) specification (Section 5.2.1 "Host Controller Enable"): > when Host Controller Enable (HCE) transitions from 1 to 0, a host > controller reset is initiated. The host controller shall abort all > active transfers, return internal state machines to idle, and de-assert > all interrupts. > > Currently, QEMU's UFS emulator only clears HCS and HCE registers upon > HCE=0, leaving internal state active. Specifically: > - Outstanding SCSI requests in the block layer are not purged. > - Active bottom halves (doorbell_bh, complete_bh, and MCQ sq/cq BHs) > remain scheduled. > - Allocated MCQ Submission and Completion Queues (sq and cq) are > not freed. > - Dynamic MCQ queue registers, legacy UTRL request states, and status > registers (UTRLCNR, UTRLRSR) remain stale. > > Implement ufs_hce_reset() to: > 1. Implement .cancel callback in ufs_scsi_info to properly unref > scsi_req and prevent reference leaks when SCSI requests are purged. > 2. Cancel active bottom halves (doorbell_bh, complete_bh, and MCQ sq/cq > BHs) and guard them with a resetting flag before purging requests, > ensuring blk_drain() cannot run or reschedule request-producing BHs. > 3. Purge outstanding SCSI requests for all logical units via > scsi_device_purge_requests(). > 4. Clear standard request list slots and release SGLs via > ufs_clear_req(), and clear doorbells and status registers (UTRLCNR, > UTRLRSR). > 5. Free allocated MCQ queues and clear dynamic queue registers while > preserving static capability offsets. > 6. De-assert interrupts via ufs_irq_check(). > 7. Add a trace_ufs_hce_reset() trace event. > > Signed-off-by: Stanley Jhu > --- Thank you for your contribution. Reviewed-by: Jeuk Kim