From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stefan.Bruens@rwth-aachen.de (=?iso-8859-1?Q?Br=FCns=2C_Stefan?=) Date: Mon, 4 Sep 2017 14:47:24 +0000 Subject: [PATCH 02/10] dmaengine: sun6i: Correct burst length field offsets for H3 In-Reply-To: <20170904075924.jufrqijrtxcqvztd@flea> References: <20170903224100.17893-1-stefan.bruens@rwth-aachen.de> <20170903224100.17893-3-stefan.bruens@rwth-aachen.de> <20170904075924.jufrqijrtxcqvztd@flea> Message-ID: <2223782.bf3lvqWUP7@sbruens-linux> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Montag, 4. September 2017 09:59:24 CEST Maxime Ripard wrote: > On Mon, Sep 04, 2017 at 12:40:53AM +0200, Stefan Br?ns wrote: > > For the H3, the burst lengths field offsets in the channel configuration > > register differs from earlier SoC generations. > > > > Using the A31 register macros actually configured the H3 controller > > do to bursts of length 1 always, which although working leads to higher > > bus utilisation. > > > > Signed-off-by: Stefan Br?ns > > --- > > > > drivers/dma/sun6i-dma.c | 28 +++++++++++++++++++++------- > > 1 file changed, 21 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c > > index 1d9b3be30d22..f1a139f0102f 100644 > > --- a/drivers/dma/sun6i-dma.c > > +++ b/drivers/dma/sun6i-dma.c > > @@ -68,13 +68,15 @@ > > > > #define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & 0x1f) > > #define DMA_CHAN_CFG_SRC_IO_MODE BIT(5) > > #define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5) > > > > -#define DMA_CHAN_CFG_SRC_BURST(x) (((x) & 0x3) << 7) > > +#define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7) > > +#define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6) > > > > #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) > > > > #define DMA_CHAN_CFG_DST_DRQ(x) (DMA_CHAN_CFG_SRC_DRQ(x) << 16) > > #define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16) > > #define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16) > > > > -#define DMA_CHAN_CFG_DST_BURST(x) (DMA_CHAN_CFG_SRC_BURST(x) << 16) > > +#define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << > > 16) +#define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) > > << 16)> > > #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16) > > > > #define DMA_CHAN_CUR_SRC 0x10 > > > > @@ -554,11 +556,17 @@ static int set_config(struct sun6i_dma_dev *sdev, > > > > if (dst_width < 0) > > > > return dst_width; > > > > - *p_cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) | > > - DMA_CHAN_CFG_SRC_WIDTH(src_width) | > > - DMA_CHAN_CFG_DST_BURST(dst_burst) | > > + *p_cfg = DMA_CHAN_CFG_SRC_WIDTH(src_width) | > > > > DMA_CHAN_CFG_DST_WIDTH(dst_width); > > > > + if (sdev->cfg->dmac_variant == DMAC_VARIANT_H3) { > > + *p_cfg |= DMA_CHAN_CFG_SRC_BURST_H3(src_burst) | > > + DMA_CHAN_CFG_DST_BURST_H3(dst_burst); > > + } else { > > + *p_cfg |= DMA_CHAN_CFG_SRC_BURST_A31(src_burst) | > > + DMA_CHAN_CFG_DST_BURST_A31(dst_burst); > > + } > > + > > I guess we have two options to support that properly. We could either > have a different function that would generate that register value > based on the parameters we have, or duplicate the set_config function > entirely, with function pointer stored in the configuration. > > I think I prefer the former, as it reduces the code duplication. Duplicating "set_config" would also mean duplicating sun6i_dma_prep_dma_memcpy - there are two hunks which change setting of the burst length register value. A function pointer in the config would work. Kind regards, Stefan From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?iso-8859-1?Q?Br=FCns=2C_Stefan?= Subject: Re: [PATCH 02/10] dmaengine: sun6i: Correct burst length field offsets for H3 Date: Mon, 4 Sep 2017 14:47:24 +0000 Message-ID: <2223782.bf3lvqWUP7@sbruens-linux> References: <20170903224100.17893-1-stefan.bruens@rwth-aachen.de> <20170903224100.17893-3-stefan.bruens@rwth-aachen.de> <20170904075924.jufrqijrtxcqvztd@flea> Reply-To: stefan.bruens-vA1bhqPz9FBZXbeN9DUtxg@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20170904075924.jufrqijrtxcqvztd@flea> Content-Language: en-US Content-ID: List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Maxime Ripard Cc: "linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "dmaengine-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Vinod Koul , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Chen-Yu Tsai , Rob Herring , Code Kipper , Andre Przywara List-Id: devicetree@vger.kernel.org On Montag, 4. September 2017 09:59:24 CEST Maxime Ripard wrote: > On Mon, Sep 04, 2017 at 12:40:53AM +0200, Stefan Br=C3=BCns wrote: > > For the H3, the burst lengths field offsets in the channel configuratio= n > > register differs from earlier SoC generations. > >=20 > > Using the A31 register macros actually configured the H3 controller > > do to bursts of length 1 always, which although working leads to higher > > bus utilisation. > >=20 > > Signed-off-by: Stefan Br=C3=BCns > > --- > >=20 > > drivers/dma/sun6i-dma.c | 28 +++++++++++++++++++++------- > > 1 file changed, 21 insertions(+), 7 deletions(-) > >=20 > > diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c > > index 1d9b3be30d22..f1a139f0102f 100644 > > --- a/drivers/dma/sun6i-dma.c > > +++ b/drivers/dma/sun6i-dma.c > > @@ -68,13 +68,15 @@ > >=20 > > #define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & 0x1f) > > #define DMA_CHAN_CFG_SRC_IO_MODE BIT(5) > > #define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5) > >=20 > > -#define DMA_CHAN_CFG_SRC_BURST(x) (((x) & 0x3) << 7) > > +#define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7) > > +#define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6) > >=20 > > #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) > > =20 > > #define DMA_CHAN_CFG_DST_DRQ(x) (DMA_CHAN_CFG_SRC_DRQ(x) << 16) > > #define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16) > > #define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << = 16) > >=20 > > -#define DMA_CHAN_CFG_DST_BURST(x) (DMA_CHAN_CFG_SRC_BURST(x) << 16) > > +#define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) <= < > > 16) +#define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) > > << 16)>=20 > > #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16) > > =20 > > #define DMA_CHAN_CUR_SRC 0x10 > >=20 > > @@ -554,11 +556,17 @@ static int set_config(struct sun6i_dma_dev *sdev, > >=20 > > if (dst_width < 0) > > =09 > > return dst_width; > >=20 > > - *p_cfg =3D DMA_CHAN_CFG_SRC_BURST(src_burst) | > > - DMA_CHAN_CFG_SRC_WIDTH(src_width) | > > - DMA_CHAN_CFG_DST_BURST(dst_burst) | > > + *p_cfg =3D DMA_CHAN_CFG_SRC_WIDTH(src_width) | > >=20 > > DMA_CHAN_CFG_DST_WIDTH(dst_width); > >=20 > > + if (sdev->cfg->dmac_variant =3D=3D DMAC_VARIANT_H3) { > > + *p_cfg |=3D DMA_CHAN_CFG_SRC_BURST_H3(src_burst) | > > + DMA_CHAN_CFG_DST_BURST_H3(dst_burst); > > + } else { > > + *p_cfg |=3D DMA_CHAN_CFG_SRC_BURST_A31(src_burst) | > > + DMA_CHAN_CFG_DST_BURST_A31(dst_burst); > > + } > > + >=20 > I guess we have two options to support that properly. We could either > have a different function that would generate that register value > based on the parameters we have, or duplicate the set_config function > entirely, with function pointer stored in the configuration. >=20 > I think I prefer the former, as it reduces the code duplication. Duplicating "set_config" would also mean duplicating sun6i_dma_prep_dma_mem= cpy=20 - there are two hunks which change setting of the burst length register val= ue. A function pointer in the config would work. Kind regards, Stefan --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753836AbdIDOr3 convert rfc822-to-8bit (ORCPT ); Mon, 4 Sep 2017 10:47:29 -0400 Received: from mail-out-2.itc.rwth-aachen.de ([134.130.5.47]:32801 "EHLO mail-out-2.itc.rwth-aachen.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753621AbdIDOr1 (ORCPT ); Mon, 4 Sep 2017 10:47:27 -0400 X-IronPort-AV: E=Sophos;i="5.41,475,1498514400"; d="scan'208";a="11738967" From: =?iso-8859-1?Q?Br=FCns=2C_Stefan?= To: Maxime Ripard CC: "linux-sunxi@googlegroups.com" , "devicetree@vger.kernel.org" , "dmaengine@vger.kernel.org" , Vinod Koul , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , Chen-Yu Tsai , Rob Herring , Code Kipper , Andre Przywara Subject: Re: [PATCH 02/10] dmaengine: sun6i: Correct burst length field offsets for H3 Thread-Topic: [PATCH 02/10] dmaengine: sun6i: Correct burst length field offsets for H3 Thread-Index: AQHTJVQjjowTXsWGTEqsv7sWe72pDaKkrUEA Date: Mon, 4 Sep 2017 14:47:24 +0000 Message-ID: <2223782.bf3lvqWUP7@sbruens-linux> References: <20170903224100.17893-1-stefan.bruens@rwth-aachen.de> <20170903224100.17893-3-stefan.bruens@rwth-aachen.de> <20170904075924.jufrqijrtxcqvztd@flea> In-Reply-To: <20170904075924.jufrqijrtxcqvztd@flea> Accept-Language: en-US, de-DE Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [78.35.13.203] Content-Type: text/plain; charset="iso-8859-1" Content-ID: Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Montag, 4. September 2017 09:59:24 CEST Maxime Ripard wrote: > On Mon, Sep 04, 2017 at 12:40:53AM +0200, Stefan Brüns wrote: > > For the H3, the burst lengths field offsets in the channel configuration > > register differs from earlier SoC generations. > > > > Using the A31 register macros actually configured the H3 controller > > do to bursts of length 1 always, which although working leads to higher > > bus utilisation. > > > > Signed-off-by: Stefan Brüns > > --- > > > > drivers/dma/sun6i-dma.c | 28 +++++++++++++++++++++------- > > 1 file changed, 21 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c > > index 1d9b3be30d22..f1a139f0102f 100644 > > --- a/drivers/dma/sun6i-dma.c > > +++ b/drivers/dma/sun6i-dma.c > > @@ -68,13 +68,15 @@ > > > > #define DMA_CHAN_CFG_SRC_DRQ(x) ((x) & 0x1f) > > #define DMA_CHAN_CFG_SRC_IO_MODE BIT(5) > > #define DMA_CHAN_CFG_SRC_LINEAR_MODE (0 << 5) > > > > -#define DMA_CHAN_CFG_SRC_BURST(x) (((x) & 0x3) << 7) > > +#define DMA_CHAN_CFG_SRC_BURST_A31(x) (((x) & 0x3) << 7) > > +#define DMA_CHAN_CFG_SRC_BURST_H3(x) (((x) & 0x3) << 6) > > > > #define DMA_CHAN_CFG_SRC_WIDTH(x) (((x) & 0x3) << 9) > > > > #define DMA_CHAN_CFG_DST_DRQ(x) (DMA_CHAN_CFG_SRC_DRQ(x) << 16) > > #define DMA_CHAN_CFG_DST_IO_MODE (DMA_CHAN_CFG_SRC_IO_MODE << 16) > > #define DMA_CHAN_CFG_DST_LINEAR_MODE (DMA_CHAN_CFG_SRC_LINEAR_MODE << 16) > > > > -#define DMA_CHAN_CFG_DST_BURST(x) (DMA_CHAN_CFG_SRC_BURST(x) << 16) > > +#define DMA_CHAN_CFG_DST_BURST_A31(x) (DMA_CHAN_CFG_SRC_BURST_A31(x) << > > 16) +#define DMA_CHAN_CFG_DST_BURST_H3(x) (DMA_CHAN_CFG_SRC_BURST_H3(x) > > << 16)> > > #define DMA_CHAN_CFG_DST_WIDTH(x) (DMA_CHAN_CFG_SRC_WIDTH(x) << 16) > > > > #define DMA_CHAN_CUR_SRC 0x10 > > > > @@ -554,11 +556,17 @@ static int set_config(struct sun6i_dma_dev *sdev, > > > > if (dst_width < 0) > > > > return dst_width; > > > > - *p_cfg = DMA_CHAN_CFG_SRC_BURST(src_burst) | > > - DMA_CHAN_CFG_SRC_WIDTH(src_width) | > > - DMA_CHAN_CFG_DST_BURST(dst_burst) | > > + *p_cfg = DMA_CHAN_CFG_SRC_WIDTH(src_width) | > > > > DMA_CHAN_CFG_DST_WIDTH(dst_width); > > > > + if (sdev->cfg->dmac_variant == DMAC_VARIANT_H3) { > > + *p_cfg |= DMA_CHAN_CFG_SRC_BURST_H3(src_burst) | > > + DMA_CHAN_CFG_DST_BURST_H3(dst_burst); > > + } else { > > + *p_cfg |= DMA_CHAN_CFG_SRC_BURST_A31(src_burst) | > > + DMA_CHAN_CFG_DST_BURST_A31(dst_burst); > > + } > > + > > I guess we have two options to support that properly. We could either > have a different function that would generate that register value > based on the parameters we have, or duplicate the set_config function > entirely, with function pointer stored in the configuration. > > I think I prefer the former, as it reduces the code duplication. Duplicating "set_config" would also mean duplicating sun6i_dma_prep_dma_memcpy - there are two hunks which change setting of the burst length register value. A function pointer in the config would work. Kind regards, Stefan