diff for duplicates of <2242962.kh0Ty0L2C4@phil> diff --git a/a/1.txt b/N1/1.txt index a6b77e7..66c3f26 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,11 +1,11 @@ -Am Dienstag, 1. M=E4rz 2016, 18:14:31 schrieb Xing Zheng: +Am Dienstag, 1. März 2016, 18:14:31 schrieb Xing Zheng: > Thers are only two parent PLLs that APLL and GPLL for core on the > previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed > GPLL as alternate parent when core is switching freq. ->=20 +> > Since RK3399 big.LITTLE architecture, we need to select and adapt > more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. ->=20 -> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> +> +> Signed-off-by: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org> note to self: looks good to go diff --git a/a/content_digest b/N1/content_digest index 58850ae..a3f6131 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,30 +1,31 @@ "ref\01456827275-8035-1-git-send-email-zhengxing@rock-chips.com\0" "ref\01456827275-8035-2-git-send-email-zhengxing@rock-chips.com\0" - "From\0Heiko Stuebner <heiko@sntech.de>\0" + "ref\01456827275-8035-2-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org\0" + "From\0Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\0" "Subject\0Re: [RESEND PATCH v2 1/5] clk: rockchip: add more mux parameters for new pll sources\0" "Date\0Wed, 09 Mar 2016 02:12:31 +0100\0" - "To\0Xing Zheng <zhengxing@rock-chips.com>\0" - "Cc\0linux-rockchip@lists.infradead.org" - huangtao@rock-chips.com - jay.xu@rock-chips.com - elaine.zhang@rock-chips.com - Michael Turquette <mturquette@baylibre.com> - Stephen Boyd <sboyd@codeaurora.org> - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " linux-kernel@vger.kernel.org\0" + "To\0Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\0" + "Cc\0huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org" + Michael Turquette <mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> + Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> + linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org + elaine.zhang-TNX95d0MmH7DzftRWevZcw@public.gmane.org + jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org + linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" - "Am Dienstag, 1. M=E4rz 2016, 18:14:31 schrieb Xing Zheng:\n" + "Am Dienstag, 1. M\303\244rz 2016, 18:14:31 schrieb Xing Zheng:\n" "> Thers are only two parent PLLs that APLL and GPLL for core on the\n" "> previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed\n" "> GPLL as alternate parent when core is switching freq.\n" - ">=20\n" + "> \n" "> Since RK3399 big.LITTLE architecture, we need to select and adapt\n" "> more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.\n" - ">=20\n" - "> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>\n" + "> \n" + "> Signed-off-by: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\n" "\n" note to self: looks good to go -f18caedbfb5bbf1fc31e8ca10f19f36f9a7ca9bb0089251eb1d782a005e1d62e +629a7a529b2de634386a8f496578463b7b635a48ee1bcc735cff835d147f7600
diff --git a/a/1.txt b/N2/1.txt index a6b77e7..01b8db4 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,11 +1,11 @@ -Am Dienstag, 1. M=E4rz 2016, 18:14:31 schrieb Xing Zheng: +Am Dienstag, 1. M?rz 2016, 18:14:31 schrieb Xing Zheng: > Thers are only two parent PLLs that APLL and GPLL for core on the > previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed > GPLL as alternate parent when core is switching freq. ->=20 +> > Since RK3399 big.LITTLE architecture, we need to select and adapt > more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. ->=20 +> > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> note to self: looks good to go diff --git a/a/content_digest b/N2/content_digest index 58850ae..38a251b 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,30 +1,21 @@ "ref\01456827275-8035-1-git-send-email-zhengxing@rock-chips.com\0" "ref\01456827275-8035-2-git-send-email-zhengxing@rock-chips.com\0" - "From\0Heiko Stuebner <heiko@sntech.de>\0" - "Subject\0Re: [RESEND PATCH v2 1/5] clk: rockchip: add more mux parameters for new pll sources\0" + "From\0heiko@sntech.de (Heiko Stuebner)\0" + "Subject\0[RESEND PATCH v2 1/5] clk: rockchip: add more mux parameters for new pll sources\0" "Date\0Wed, 09 Mar 2016 02:12:31 +0100\0" - "To\0Xing Zheng <zhengxing@rock-chips.com>\0" - "Cc\0linux-rockchip@lists.infradead.org" - huangtao@rock-chips.com - jay.xu@rock-chips.com - elaine.zhang@rock-chips.com - Michael Turquette <mturquette@baylibre.com> - Stephen Boyd <sboyd@codeaurora.org> - linux-clk@vger.kernel.org - linux-arm-kernel@lists.infradead.org - " linux-kernel@vger.kernel.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" - "Am Dienstag, 1. M=E4rz 2016, 18:14:31 schrieb Xing Zheng:\n" + "Am Dienstag, 1. M?rz 2016, 18:14:31 schrieb Xing Zheng:\n" "> Thers are only two parent PLLs that APLL and GPLL for core on the\n" "> previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed\n" "> GPLL as alternate parent when core is switching freq.\n" - ">=20\n" + "> \n" "> Since RK3399 big.LITTLE architecture, we need to select and adapt\n" "> more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.\n" - ">=20\n" + "> \n" "> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>\n" "\n" note to self: looks good to go -f18caedbfb5bbf1fc31e8ca10f19f36f9a7ca9bb0089251eb1d782a005e1d62e +fbaa265205a8ee90fe9ca5cf1f25aab9d6b75f2dd6af2593588069665ecf6d3a
diff --git a/a/1.txt b/N3/1.txt index a6b77e7..496748b 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -1,11 +1,11 @@ -Am Dienstag, 1. M=E4rz 2016, 18:14:31 schrieb Xing Zheng: +Am Dienstag, 1. März 2016, 18:14:31 schrieb Xing Zheng: > Thers are only two parent PLLs that APLL and GPLL for core on the > previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed > GPLL as alternate parent when core is switching freq. ->=20 +> > Since RK3399 big.LITTLE architecture, we need to select and adapt > more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources. ->=20 +> > Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> note to self: looks good to go diff --git a/a/content_digest b/N3/content_digest index 58850ae..2686884 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -15,16 +15,16 @@ " linux-kernel@vger.kernel.org\0" "\00:1\0" "b\0" - "Am Dienstag, 1. M=E4rz 2016, 18:14:31 schrieb Xing Zheng:\n" + "Am Dienstag, 1. M\303\244rz 2016, 18:14:31 schrieb Xing Zheng:\n" "> Thers are only two parent PLLs that APLL and GPLL for core on the\n" "> previous SoCs (RK3066/RK3188/RK3288/RK3368). Hence, we set fixed\n" "> GPLL as alternate parent when core is switching freq.\n" - ">=20\n" + "> \n" "> Since RK3399 big.LITTLE architecture, we need to select and adapt\n" "> more PLLs (ALPLL/ABPLL/DPLL/GPLL) sources.\n" - ">=20\n" + "> \n" "> Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>\n" "\n" note to self: looks good to go -f18caedbfb5bbf1fc31e8ca10f19f36f9a7ca9bb0089251eb1d782a005e1d62e +7ee38546647b6e3326b79d2c608ffa1eab6f4231eba5ed10f3489510f8b97fc8
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