diff for duplicates of <2268000.l71DRbJSRE@wasted.cogentembedded.com> diff --git a/a/1.txt b/N1/1.txt index 006b8ff..3a0de55 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -51,7 +51,7 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + #address-cells = <1>; + #size-cells = <0>; + -+ cpu0: cpu@0 { ++ cpu0: cpu at 0 { + device_type = "cpu"; + compatible = "arm,cortex-a15"; + reg = <0>; @@ -61,7 +61,7 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + next-level-cache = <&L2_CA15>; + }; + -+ L2_CA15: cache-controller@0 { ++ L2_CA15: cache-controller at 0 { + compatible = "cache"; + reg = <0>; + cache-unified; @@ -78,7 +78,7 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + #size-cells = <2>; + ranges; + -+ gic: interrupt-controller@f1001000 { ++ gic: interrupt-controller at f1001000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; @@ -102,14 +102,14 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + IRQ_TYPE_LEVEL_LOW)>; + }; + -+ sysc: system-controller@e6180000 { ++ sysc: system-controller at e6180000 { + compatible = "renesas,r8a7792-sysc"; + reg = <0 0xe6180000 0 0x0200>; + #power-domain-cells = <1>; + }; + + /* Special CPG clocks */ -+ cpg_clocks: cpg_clocks@e6150000 { ++ cpg_clocks: cpg_clocks at e6150000 { + compatible = "renesas,r8a7792-cpg-clocks", + "renesas,rcar-gen2-cpg-clocks"; + reg = <0 0xe6150000 0 0x1000>; @@ -121,7 +121,7 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + }; + + /* Gate clocks */ -+ mstp2_clks: mstp2_clks@e6150138 { ++ mstp2_clks: mstp2_clks at e6150138 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; @@ -132,7 +132,7 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + >; + clock-output-names = "sys-dmac1", "sys-dmac0"; + }; -+ mstp4_clks: mstp4_clks@e6150140 { ++ mstp4_clks: mstp4_clks at e6150140 { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; @@ -141,7 +141,7 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + clock-indices = <R8A7792_CLK_IRQC>; + clock-output-names = "irqc"; + }; -+ mstp7_clks: mstp7_clks@e615014c { ++ mstp7_clks: mstp7_clks at e615014c { + compatible = "renesas,r8a7792-mstp-clocks", + "renesas,cpg-mstp-clocks"; + reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; diff --git a/a/content_digest b/N1/content_digest index 4a28fcc..4c3e9ff 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,18 +1,8 @@ "ref\03446154.oZ24315zaL@wasted.cogentembedded.com\0" - "From\0Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>\0" + "From\0sergei.shtylyov@cogentembedded.com (Sergei Shtylyov)\0" "Subject\0[PATCH v2 05/11] ARM: dts: r8a7792: initial SoC device tree\0" "Date\0Sat, 04 Jun 2016 00:26:10 +0300\0" - "To\0horms@verge.net.au" - linux-renesas-soc@vger.kernel.org - robh+dt@kernel.org - pawel.moll@arm.com - mark.rutland@arm.com - ijc+devicetree@hellion.org.uk - galak@codeaurora.org - " devicetree@vger.kernel.org\0" - "Cc\0magnus.damm@gmail.com" - linux@arm.linux.org.uk - " linux-arm-kernel@lists.infradead.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "The initial R8A7792 SoC device tree including CPU core, GIC, timer, SYSC,\n" @@ -68,7 +58,7 @@ "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tcpu0: cpu@0 {\n" + "+\t\tcpu0: cpu at 0 {\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\tcompatible = \"arm,cortex-a15\";\n" "+\t\t\treg = <0>;\n" @@ -78,7 +68,7 @@ "+\t\t\tnext-level-cache = <&L2_CA15>;\n" "+\t\t};\n" "+\n" - "+\t\tL2_CA15: cache-controller@0 {\n" + "+\t\tL2_CA15: cache-controller at 0 {\n" "+\t\t\tcompatible = \"cache\";\n" "+\t\t\treg = <0>;\n" "+\t\t\tcache-unified;\n" @@ -95,7 +85,7 @@ "+\t\t#size-cells = <2>;\n" "+\t\tranges;\n" "+\n" - "+\t\tgic: interrupt-controller@f1001000 {\n" + "+\t\tgic: interrupt-controller at f1001000 {\n" "+\t\t\tcompatible = \"arm,gic-400\";\n" "+\t\t\t#interrupt-cells = <3>;\n" "+\t\t\tinterrupt-controller;\n" @@ -119,14 +109,14 @@ "+\t\t\t\t IRQ_TYPE_LEVEL_LOW)>;\n" "+\t\t};\n" "+\n" - "+\t\tsysc: system-controller@e6180000 {\n" + "+\t\tsysc: system-controller at e6180000 {\n" "+\t\t\tcompatible = \"renesas,r8a7792-sysc\";\n" "+\t\t\treg = <0 0xe6180000 0 0x0200>;\n" "+\t\t\t#power-domain-cells = <1>;\n" "+\t\t};\n" "+\n" "+\t\t/* Special CPG clocks */\n" - "+\t\tcpg_clocks: cpg_clocks@e6150000 {\n" + "+\t\tcpg_clocks: cpg_clocks at e6150000 {\n" "+\t\t\tcompatible = \"renesas,r8a7792-cpg-clocks\",\n" "+\t\t\t\t \"renesas,rcar-gen2-cpg-clocks\";\n" "+\t\t\treg = <0 0xe6150000 0 0x1000>;\n" @@ -138,7 +128,7 @@ "+\t\t};\n" "+\n" "+\t\t/* Gate clocks */\n" - "+\t\tmstp2_clks: mstp2_clks@e6150138 {\n" + "+\t\tmstp2_clks: mstp2_clks at e6150138 {\n" "+\t\t\tcompatible = \"renesas,r8a7792-mstp-clocks\",\n" "+\t\t\t\t \"renesas,cpg-mstp-clocks\";\n" "+\t\t\treg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;\n" @@ -149,7 +139,7 @@ "+\t\t\t>;\n" "+\t\t\tclock-output-names = \"sys-dmac1\", \"sys-dmac0\";\n" "+\t\t};\n" - "+\t\tmstp4_clks: mstp4_clks@e6150140 {\n" + "+\t\tmstp4_clks: mstp4_clks at e6150140 {\n" "+\t\t\tcompatible = \"renesas,r8a7792-mstp-clocks\",\n" "+\t\t\t\t \"renesas,cpg-mstp-clocks\";\n" "+\t\t\treg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;\n" @@ -158,7 +148,7 @@ "+\t\t\tclock-indices = <R8A7792_CLK_IRQC>;\n" "+\t\t\tclock-output-names = \"irqc\";\n" "+\t\t};\n" - "+\t\tmstp7_clks: mstp7_clks@e615014c {\n" + "+\t\tmstp7_clks: mstp7_clks at e615014c {\n" "+\t\t\tcompatible = \"renesas,r8a7792-mstp-clocks\",\n" "+\t\t\t\t \"renesas,cpg-mstp-clocks\";\n" "+\t\t\treg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;\n" @@ -216,4 +206,4 @@ "+\t};\n" +}; -5728e04412445d3671f92f520c6d5e81e55b2362512d316201c9d236c5222f0e +ee19524181a2fa305d07b2d28becaa5536284f07043b6ead1c91b3b660154784
diff --git a/a/1.txt b/N2/1.txt index 006b8ff..083a294 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,7 +1,7 @@ The initial R8A7792 SoC device tree including CPU core, GIC, timer, SYSC, and the required clock descriptions. -Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> +Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org> --- Changes in version 2: @@ -198,3 +198,8 @@ Index: renesas/arch/arm/boot/dts/r8a7792.dtsi + clock-mult = <1>; + }; +}; + +-- +To unsubscribe from this list: send the line "unsubscribe devicetree" in +the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org +More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N2/content_digest index 4a28fcc..d3f996b 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,24 +1,25 @@ "ref\03446154.oZ24315zaL@wasted.cogentembedded.com\0" - "From\0Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>\0" + "ref\03446154.oZ24315zaL-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org\0" + "From\0Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>\0" "Subject\0[PATCH v2 05/11] ARM: dts: r8a7792: initial SoC device tree\0" "Date\0Sat, 04 Jun 2016 00:26:10 +0300\0" - "To\0horms@verge.net.au" - linux-renesas-soc@vger.kernel.org - robh+dt@kernel.org - pawel.moll@arm.com - mark.rutland@arm.com - ijc+devicetree@hellion.org.uk - galak@codeaurora.org - " devicetree@vger.kernel.org\0" - "Cc\0magnus.damm@gmail.com" - linux@arm.linux.org.uk - " linux-arm-kernel@lists.infradead.org\0" + "To\0horms-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org" + linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org + robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org + pawel.moll-5wv7dgnIgG8@public.gmane.org + mark.rutland-5wv7dgnIgG8@public.gmane.org + ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org + galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org + " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "Cc\0magnus.damm-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org" + linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org + " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" "\00:1\0" "b\0" "The initial R8A7792 SoC device tree including CPU core, GIC, timer, SYSC,\n" "and the required clock descriptions.\n" "\n" - "Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>\n" + "Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>\n" "\n" "---\n" "Changes in version 2:\n" @@ -214,6 +215,11 @@ "+\t\tclock-div = <3>;\n" "+\t\tclock-mult = <1>;\n" "+\t};\n" - +}; + "+};\n" + "\n" + "--\n" + "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" + "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" + More majordomo info at http://vger.kernel.org/majordomo-info.html -5728e04412445d3671f92f520c6d5e81e55b2362512d316201c9d236c5222f0e +939012ff7a518b184e38fb4f87f9b645d884ba6af97d2b69ab4e4e75a37c7402
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