From: rk1825 <rk1825@rediffmail.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] Board Reset issue
Date: Tue, 31 Mar 2009 04:20:02 -0700 (PDT) [thread overview]
Message-ID: <22803060.post@talk.nabble.com> (raw)
In-Reply-To: <D7CCA83BB0796C49BC0BB53B6AB120891E794E@zch01exm21.fsl.freescale.net>
Liu Dave wrote:
>
>> I am using a custom board with MPC8313E processor. In u-boot
>> prompt, when i
>> do TFTP of large size files, sometime it hangs completely
>> and, sometimes it
>> says bus fault, prints following message and resets the board.
>>
>> /////////////////////////////////////////////////message
>> printed/////////////////////////////////////////////////
>> Bus Fault @ 0x00000900, fixup 0x00000000
>> Machine check in kernel mode.
>> Caused by (from msr): regs 07f85b48 Unknown values in msr
>> NIP: 00000900 XER: 20000000 LR: 07FC709C REGS: 07f85b48 TRAP:
>> 0200 DAR:
>> 07F85F58
>> MSR: 00001000 EE: 0 PR: 0 FP: 0 ME: 1 IR/DR: 00
>>
>> GPR00: 00000000 07F85C38 00000080 FFFFFFFF 07FFCD80 07FEDB88 07FEDB88
>> 07FED124
>> GPR08: 07FEDB98 4E800020 07FEDBB0 0000000C 07F85B28 F54ADC0C 07FF0000
>> 09FA8000
>> GPR16: 7347FB13 00000000 00000000 00000000 00000000 00000000 00000000
>> 00000000
>> GPR24: 07F89ED8 00000000 07F85FBC 00000003 00000000 07F85F58 0FFF1390
>> 07FED054
>> Call backtrace:
>> 07FC70D4 07FC7274 07FC73F8 07FAE0E8 07FC4724 07FCBDDC 07FCB4D0
>> 07FCB6DC 07FBAAC4 07FCBDDC 07FCB4D0 07FCB62C 07FBA2B4 07FAC84C
>> 07FAB66C 00420400
>> machine check
>> Resetting the board.
>> //////////////////////////////////////////////////////////////
>> /////////////////////////////////////////////////
>>
>> Please help me with what could be the reason for this ?
>
> Did you have one stable memory system?
>
> What is the clock information? Such as core/csb/ddr data rate?
> What is the ACR value?
>
> Thanks, Dave
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
>
>
DDR2 is used in our board with following clock configuration:-
Clock configuration:
Coherent System Bus: 166 MHz
Core: 333 MHz
Local Bus Controller: 166 MHz
Local Bus: 41 MHz
DDR: 333 MHz
SEC: 55 MHz
I2C1: 166 MHz
I2C2: 166 MHz
TSEC1: 166 MHz
TSEC2: 166 MHz
USB MPH: 0 MHz
USB DR: 55 MHz
CPU: MPC8313E, Rev: 10 at 333.333 MHz
Board: S600 CPU BOARD
I2C: ready
DRAM: Initializing
DDR RAM: 128 MB
ACR settings defined are as follows:-
Arbiter pipeline depth (0-3)
Arbiter repeat count (0-7)
Thanks
Rupesh
--
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Sent from the Uboot - Users mailing list archive at Nabble.com.
prev parent reply other threads:[~2009-03-31 11:20 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-03-31 11:02 [U-Boot] Board Reset issue rk1825
2009-03-31 11:06 ` Liu Dave-R63238
2009-03-31 11:20 ` rk1825 [this message]
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