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[2001:4c4e:24cd:7200:f6bb:a872:344e:1a32]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4950871e830sm145205475e9.2.2026.07.15.03.45.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jul 2026 03:45:43 -0700 (PDT) From: Timur =?UTF-8?B?S3Jpc3TDs2Y=?= To: amd-gfx@lists.freedesktop.org, Alex Deucher , christian.koenig@amd.com, pierre-eric.pelloux-prayer@amd.com, Natalie Vock , Tvrtko Ursulin Subject: Re: [PATCH 7/9] drm/amdgpu/gfx7: Use COND_EXEC Date: Wed, 15 Jul 2026 12:45:42 +0200 Message-ID: <2299222.Hq7AAxBmiT@timur-max> In-Reply-To: <2a8374ee-bd72-4306-9524-a8cb3cc0d5f8@ursulin.net> References: <20260713125838.30607-1-timur.kristof@gmail.com> <20260713125838.30607-8-timur.kristof@gmail.com> <2a8374ee-bd72-4306-9524-a8cb3cc0d5f8@ursulin.net> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" On 2026. j=C3=BAlius 15., szerda 11:38:40 k=C3=B6z=C3=A9p-eur=C3=B3pai ny= =C3=A1ri id=C5=91 Tvrtko Ursulin=20 wrote: > On 13/07/2026 13:58, Timur Krist=C3=B3f wrote: > > COND_EXEC tells the CP to discard the dwords following it > > when its condition is zero (false). > >=20 > > This is useful for GPU recovery because it can help reduce > > collateral damage during GFX IP block soft reset, meaning > > that it reduces the likelyhood that we fail some jobs which > > are not guilty of the hang as the IP block soft reset > > mechanism clears the condition before doing the reset. > >=20 > > Signed-off-by: Timur Krist=C3=B3f > > --- > >=20 > > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 22 ++++++++++++++++++++++ > > 1 file changed, 22 insertions(+) > >=20 > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c index 915612628f9a..6d52b8710437 > > 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > > @@ -3162,6 +3162,22 @@ static void gfx_v7_0_ring_emit_vm_flush(struct > > amdgpu_ring *ring,>=20 > > } > > =20 > > } > >=20 > > +static unsigned int gfx_v7_0_ring_emit_init_cond_exec(struct amdgpu_ri= ng > > *ring, + =20 uint64_t gpu_addr) > > +{ > > + unsigned int ret; > > + > > + /* Discard following DWs after this packet when gpu_addr=3D=3D0 */ > > + amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3)); > > + amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); > > + amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); > > + amdgpu_ring_write(ring, 0); > > + ret =3D ring->wptr & ring->buf_mask; > > + /* patch dummy value later */ > > + amdgpu_ring_write(ring, 0); > > + return ret; > > +} > > + > >=20 > > static void gfx_v7_0_ring_emit_wreg(struct amdgpu_ring *ring, > > =20 > > uint32_t reg, uint32_t val) > > =20 > > { > >=20 > > @@ -4943,6 +4959,8 @@ static const struct amdgpu_ring_funcs > > gfx_v7_0_ring_funcs_gfx =3D {>=20 > > .get_wptr =3D gfx_v7_0_ring_get_wptr_gfx, > > .set_wptr =3D gfx_v7_0_ring_set_wptr_gfx, > > .emit_frame_size =3D > >=20 > > + 5 + /* gfx_v7_0_ring_emit_init_cond_exec (from=20 amdgpu_ib_schedule) */ > > + 5 + /* gfx_v7_0_ring_emit_init_cond_exec (from=20 amdgpu_vm_flush) */ >=20 > gfx8 version /appears/ to make an effort to keep the additions here > sorted in the emission order. I think at least. As far as I see it was already not in emission order here. > Not sure how much value > it adds since the whole emit_frame_size mechanism is "fragilotedious". >=20 > :) Another task for a rainy day - we see if it can be replaced with >=20 > something more manageable. If you have ideas how to clean it up, I'd be happy to hear it. > Anyway, digressions aside: >=20 > Reviewed-by: Tvrtko Ursulin >=20 > Regards, >=20 > Tvrtko >=20 > > 20 + /* gfx_v7_0_ring_emit_gds_switch */ > > 7 + /* gfx_v7_0_ring_emit_hdp_flush */ > > 5 + /* hdp invalidate */ > >=20 > > @@ -4965,6 +4983,7 @@ static const struct amdgpu_ring_funcs > > gfx_v7_0_ring_funcs_gfx =3D {>=20 > > .pad_ib =3D amdgpu_ring_generic_pad_ib, > > .emit_switch_buffer =3D gfx_v7_0_ring_emit_sb, > > .emit_cntxcntl =3D gfx_v7_ring_emit_cntxcntl, > >=20 > > + .init_cond_exec =3D gfx_v7_0_ring_emit_init_cond_exec, > >=20 > > .emit_wreg =3D gfx_v7_0_ring_emit_wreg, > > .soft_recovery =3D gfx_v7_0_ring_soft_recovery, > > .emit_mem_sync =3D gfx_v7_0_emit_mem_sync, > >=20 > > @@ -4979,6 +4998,8 @@ static const struct amdgpu_ring_funcs > > gfx_v7_0_ring_funcs_compute =3D {>=20 > > .get_wptr =3D gfx_v7_0_ring_get_wptr_compute, > > .set_wptr =3D gfx_v7_0_ring_set_wptr_compute, > > .emit_frame_size =3D > >=20 > > + 5 + /* gfx_v7_0_ring_emit_init_cond_exec (from=20 amdgpu_ib_schedule) */ > > + 5 + /* gfx_v7_0_ring_emit_init_cond_exec (from=20 amdgpu_vm_flush) */ > >=20 > > 20 + /* gfx_v7_0_ring_emit_gds_switch */ > > 7 + /* gfx_v7_0_ring_emit_hdp_flush */ > > 5 + /* hdp invalidate */ > >=20 > > @@ -4997,6 +5018,7 @@ static const struct amdgpu_ring_funcs > > gfx_v7_0_ring_funcs_compute =3D {>=20 > > .test_ib =3D gfx_v7_0_ring_test_ib, > > .insert_nop =3D amdgpu_ring_insert_nop, > > .pad_ib =3D amdgpu_ring_generic_pad_ib, > >=20 > > + .init_cond_exec =3D gfx_v7_0_ring_emit_init_cond_exec, > >=20 > > .emit_wreg =3D gfx_v7_0_ring_emit_wreg, > > .soft_recovery =3D gfx_v7_0_ring_soft_recovery, > > .emit_mem_sync =3D gfx_v7_0_emit_mem_sync_compute,