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[86.49.110.70]) by smtp.gmail.com with ESMTPSA id d9sm23516406wrn.72.2019.03.18.19.08.19 (version=TLS1_3 cipher=AEAD-AES128-GCM-SHA256 bits=128/128); Mon, 18 Mar 2019 19:08:20 -0700 (PDT) Subject: Re: [PATCH 2/3] PCI: rcar: Allow 64bit MSI addresses To: Geert Uytterhoeven Cc: Wolfram Sang , linux-pci , Marek Vasut , Phil Edworthy , Simon Horman , Linux-Renesas References: <20190317000608.24881-1-marek.vasut@gmail.com> <20190317000608.24881-2-marek.vasut@gmail.com> <20190317091228.GB2268@kunai> <940fd646-0049-890a-ac00-8bc9361b2431@gmail.com> From: Marek Vasut Openpgp: preference=signencrypt Message-ID: <22e66804-574a-ed5a-e04e-00c8a29e9dc3@gmail.com> Date: Tue, 19 Mar 2019 02:16:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.4.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org On 3/18/19 10:30 AM, Geert Uytterhoeven wrote: > Hi Marek, > > On Mon, Mar 18, 2019 at 9:39 AM Geert Uytterhoeven wrote: >> On Mon, Mar 18, 2019 at 12:39 AM Marek Vasut wrote: >>> On 3/17/19 10:12 AM, Wolfram Sang wrote: >>>> On Sun, Mar 17, 2019 at 01:06:07AM +0100, marek.vasut@gmail.com wrote: >>>>> From: Marek Vasut >>>>> >>>>> The MSI address can be 64bit. Switch the data type used to hold the >>>>> result of virt_to_phys() to phys_addr_t to reflect it's properties >>>>> correctly and program the top 32bits of PA into PCIEMSIAUR. >>>>> >>>>> Signed-off-by: Marek Vasut >>>> >>>> Looks sane. Not being a PCI expert, I wonder: Were we just lucky to not >>>> hit a 64-bit MSI address before? >>> >>> I wonder about that, virt_to_phys(__get_free_pages(GFP_KERNEL, 0)) would >>> happily return 64bit address, but with the cards I tested (a few intel >>> NICs [igb, e1000e], PCIe NVME SSDs and xHCI HCD), I am getting the MSIs >>> either way. >> >> No doubt you would be receiving the MSIs, if you have RAM at the truncated >> address, but wouldn't that cause memory corruption? >> >> Fixes: 290c1fb358605402 ("PCI: rcar: Add MSI support for PCIe") >> >> When MSI support was added, only R-Car H1 and Gen2 were supported. >> H1 doesn't have LPAE. Gen2 has, but it might have been disabled. > > Correction: as this is always mapped kernel memory, LPAE doesn't matter. > So the bug matters for arm64 only. And since the address is in the 0x7_3xxx_xxxx range on H3 S-XS, there is no visible memory corruption. Joy ... -- Best regards, Marek Vasut