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From: "Heiko Stübner" <heiko@sntech.de>
To: Andrew Jones <ajones@ventanamicro.com>, linux-riscv@lists.infradead.org
Cc: panqinglin2020@iscas.ac.cn, palmer@dabbelt.com,
	linux-riscv@lists.infradead.org, jeff@riscv.org,
	xuyinan@ict.ac.cn, Conor Dooley <conor@kernel.org>
Subject: Re: [PATCH v5 1/4] mm: modify pte format for Svnapot
Date: Wed, 05 Oct 2022 11:52:50 +0200	[thread overview]
Message-ID: <2317598.NG923GbCHz@diego> (raw)
In-Reply-To: <Yzx8YfVUmHc/3CJl@spud>

Am Dienstag, 4. Oktober 2022, 20:33:05 CEST schrieb Conor Dooley:
> On Tue, Oct 04, 2022 at 07:00:27PM +0200, Andrew Jones wrote:
> > On Mon, Oct 03, 2022 at 09:47:18PM +0800, panqinglin2020@iscas.ac.cn wrote:
> > > From: Qinglin Pan <panqinglin2020@iscas.ac.cn>
> > > 
> > > This commit adds two erratas to enable/disable svnapot support, patches
> > > code dynamicly when "svnapot" is in the "riscv,isa" field of fdt and
> > > SVNAPOT compile option is set. It will influence the behavior of
> > > has_svnapot function and pte_pfn function. All code dependent on svnapot
> > > should make sure that has_svnapot return true firstly.
> > > 
> > > Also, this commit modifies PTE definition for Svnapot, and creates some
> > > functions in pgtable.h to mark a PTE as napot and check if it is a Svnapot
> > > PTE. Until now, only 64KB napot size is supported in draft spec, so some
> > > macros has only 64KB version.
> > > 
> > > Signed-off-by: Qinglin Pan <panqinglin2020@iscas.ac.cn>

[...]

> > > +	switch (stage) {
> > > +	case RISCV_ALTERNATIVES_EARLY_BOOT:
> > > +		return false;
> > > +	default:
> > > +		return riscv_isa_extension_available(NULL, SVNAPOT);
> > > +	}
> > > +#endif
> > > +
> > > +	return false;
> > > +}
> > > +
> > >  /*
> > >   * Probe presence of individual extensions.
> > >   *
> > > @@ -301,6 +316,9 @@ static u32 __init_or_module cpufeature_probe(unsigned int stage)
> > >  	if (cpufeature_probe_zicbom(stage))
> > >  		cpu_req_feature |= (1U << CPUFEATURE_ZICBOM);
> 
> While in the area, could this be converted to BIT(CPUFEATURE_ZICBOM)?

It already is [0], although it looks like I need to ping Palmer about
that series.


Heiko

[0] https://lore.kernel.org/all/20220905111027.2463297-5-heiko@sntech.de/



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  parent reply	other threads:[~2022-10-05  9:53 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-03 13:47 [PATCH v5 0/4] riscv, mm: detect svnapot cpu support at runtime panqinglin2020
2022-10-03 13:47 ` [PATCH v5 1/4] mm: modify pte format for Svnapot panqinglin2020
2022-10-04 17:00   ` Andrew Jones
2022-10-04 17:09     ` Conor Dooley
2022-10-04 18:33     ` Conor Dooley
2022-10-05  4:43       ` Qinglin Pan
2022-10-05  6:57         ` Conor Dooley
2022-10-05  7:15         ` Andrew Jones
2022-10-05 12:41           ` Qinglin Pan
2022-10-05 13:25             ` Andrew Jones
2022-10-05 14:50               ` Qinglin Pan
2022-10-05  9:52       ` Heiko Stübner [this message]
2022-10-03 13:47 ` [PATCH v5 2/4] mm: support Svnapot in physical page linear-mapping panqinglin2020
2022-10-04 18:40   ` Conor Dooley
2022-10-05  2:43     ` Qinglin Pan
2022-10-05 11:19   ` Andrew Jones
2022-10-05 12:45     ` Qinglin Pan
2022-10-03 13:47 ` [PATCH v5 3/4] mm: support Svnapot in hugetlb page panqinglin2020
2022-10-04 18:43   ` Conor Dooley
2022-10-05  2:31     ` Qinglin Pan
2022-10-05 13:11   ` Andrew Jones
2022-10-05 14:54     ` Qinglin Pan
2022-10-03 13:47 ` [PATCH v5 4/4] mm: support Svnapot in huge vmap panqinglin2020
2022-10-04 18:46   ` Conor Dooley
2022-10-05  4:44     ` Qinglin Pan
2022-10-03 13:53 ` [PATCH v5 0/4] riscv, mm: detect svnapot cpu support at runtime Qinglin Pan

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