Re: [PATCH v2 18/23] staging: media: tegra-video: tegra20: increase maximum VI clock frequency

[Mikko Perttunen <mperttunen@nvidia.com>]

On Saturday, September 6, 2025 10:53 PM Svyatoslav Ryhel wrote:
> Increase maximum VI clock frequency to 450MHz to allow correct work with
> high resolution camera sensors.
> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> ---
>  drivers/staging/media/tegra-video/tegra20.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/media/tegra-video/tegra20.c
> index e0da496bb50f..3c5bafebfcd8 100644
> --- a/drivers/staging/media/tegra-video/tegra20.c
> +++ b/drivers/staging/media/tegra-video/tegra20.c
> @@ -590,7 +590,7 @@ const struct tegra_vi_soc tegra20_vi_soc = {
>  	.ops = &tegra20_vi_ops,
>  	.hw_revision = 1,
>  	.vi_max_channels = 2, /* TEGRA_VI_OUT_1 and TEGRA_VI_OUT_2 */
> -	.vi_max_clk_hz = 150000000,
> +	.vi_max_clk_hz = 450000000,
>  	.has_h_v_flip = true,
>  };
>  
> 

Where does the 450MHz come from? Instead of hardcoding this value for each SoC, could we just clk_set_rate(ULONG_MAX) like e.g. the vic driver does, or does that get a too high rate?