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From: Heiko =?ISO-8859-1?Q?St=FCbner?= <heiko@sntech.de>
To: qemu-devel@nongnu.org
Cc: Alistair Francis <alistair.francis@wdc.com>,
 Atish Patra <atishp@rivosinc.com>, Bin Meng <bin.meng@windriver.com>,
 Palmer Dabbelt <palmer@dabbelt.com>, qemu-riscv@nongnu.org,
 frank.chang@sifive.com, Atish Patra <atishp@rivosinc.com>
Subject: Re: [PATCH v10 10/12] target/riscv: Add few cache related PMU events
Date: Thu, 14 Jul 2022 11:55:13 +0200
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Am Dienstag, 21. Juni 2022, 01:16:00 CEST schrieb Atish Patra:
> From: Atish Patra <atish.patra@wdc.com>
> 
> Qemu can monitor the following cache related PMU events through
> tlb_fill functions.
> 
> 1. DTLB load/store miss
> 3. ITLB prefetch miss
> 
> Increment the PMU counter in tlb_fill function.
> 
> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> Signed-off-by: Atish Patra <atish.patra@wdc.com>
> Signed-off-by: Atish Patra <atishp@rivosinc.com>

Tested-by: Heiko Stuebner <heiko@sntech.de>