diff for duplicates of <2396201.CBcovI4jc4@phil> diff --git a/a/1.txt b/N1/1.txt index 7ccbb18..9f02232 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,7 +1,7 @@ Hi Jianqun, Am Mittwoch, 17. Februar 2016, 10:01:16 schrieb jianqun.xu: -> From: Xu Jianqun <jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> +> From: Xu Jianqun <jay.xu@rock-chips.com> > > Add dtsi file for Rockchip rk3399 SoCs, which includes some > general nodes such as cpu, pmu, cru, gic, amba and so on. @@ -10,7 +10,7 @@ Am Mittwoch, 17. Februar 2016, 10:01:16 schrieb jianqun.xu: please remove any review-cruft like Change-Ids from mainline patches :-) -> Signed-off-by: Xu Jianqun <jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> +> Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> > --- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 989 > +++++++++++++++++++++++++++++++ 1 file changed, 989 insertions(+) @@ -131,7 +131,7 @@ arch_cpu_idle(), which already does WFI handling even on arm64. > + -> + cpu_l0: cpu@0 { +> + cpu_l0: cpu at 0 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x0>; @@ -143,7 +143,7 @@ that won't compile, as the referenced node is not present > + enable-method = "psci"; > + }; > + -> + cpu_l1: cpu@1 { +> + cpu_l1: cpu at 1 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x1>; @@ -151,7 +151,7 @@ that won't compile, as the referenced node is not present > + enable-method = "psci"; > + }; > + -> + cpu_l2: cpu@2 { +> + cpu_l2: cpu at 2 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x2>; @@ -159,7 +159,7 @@ that won't compile, as the referenced node is not present > + enable-method = "psci"; > + }; > + -> + cpu_l3: cpu@3 { +> + cpu_l3: cpu at 3 { > + device_type = "cpu"; > + compatible = "arm,cortex-a53", "arm,armv8"; > + reg = <0x0 0x3>; @@ -167,7 +167,7 @@ that won't compile, as the referenced node is not present > + enable-method = "psci"; > + }; > + -> + cpu_b0: cpu@100 { +> + cpu_b0: cpu at 100 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x0 0x100>; @@ -175,7 +175,7 @@ that won't compile, as the referenced node is not present > + enable-method = "psci"; > + }; > + -> + cpu_b1: cpu@101 { +> + cpu_b1: cpu at 101 { > + device_type = "cpu"; > + compatible = "arm,cortex-a72", "arm,armv8"; > + reg = <0x0 0x101>; @@ -216,7 +216,7 @@ shouldn't that be GIC_CPU_MASK_SIMPLE(6) instead of 4? > + clock-output-names = "xin24m"; > + }; > + -> + gic: interrupt-controller@fee00000 { +> + gic: interrupt-controller at fee00000 { > + compatible = "arm,gic-v3"; > + #interrupt-cells = <3>; > + #address-cells = <2>; @@ -235,7 +235,7 @@ shouldn't that be GIC_CPU_MASK_SIMPLE(6) instead of 4? again GIC_CPU_MASK_SIMPLE(6)? -> + its: interrupt-controller@fee20000 { +> + its: interrupt-controller at fee20000 { > + compatible = "arm,gic-v3-its"; > + msi-controller; > + reg = <0x0 0xfee20000 0x0 0x20000>; @@ -248,7 +248,7 @@ again GIC_CPU_MASK_SIMPLE(6)? > + #size-cells = <2>; > + ranges; > + -> + dmac_bus: dma-controller@ff6d0000 { +> + dmac_bus: dma-controller at ff6d0000 { > + compatible = "arm,pl330", "arm,primecell"; > + reg = <0x0 0xff6d0000 0x0 0x4000>; > + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, @@ -266,7 +266,3 @@ rest looks nice on first glance :-) Heiko --- -To unsubscribe from this list: send the line "unsubscribe devicetree" in -the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org -More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N1/content_digest index 889ca71..9190cb8 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,33 +1,15 @@ "ref\01455673992-16469-1-git-send-email-jay.xu@rock-chips.com\0" "ref\01455674476-16655-1-git-send-email-jay.xu@rock-chips.com\0" - "ref\01455674476-16655-1-git-send-email-jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org\0" - "From\0Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\0" - "Subject\0Re: [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399\0" + "From\0heiko@sntech.de (Heiko Stuebner)\0" + "Subject\0[PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399\0" "Date\0Wed, 17 Feb 2016 08:00:33 +0100\0" - "To\0jianqun.xu <jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\0" - "Cc\0robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" - pawel.moll-5wv7dgnIgG8@public.gmane.org - mark.rutland-5wv7dgnIgG8@public.gmane.org - ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org - galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - jwerner-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org - broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org - catalin.marinas-5wv7dgnIgG8@public.gmane.org - will.deacon-5wv7dgnIgG8@public.gmane.org - sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - sjoerd.simons-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org - huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org - linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Jianqun,\n" "\n" "Am Mittwoch, 17. Februar 2016, 10:01:16 schrieb jianqun.xu:\n" - "> From: Xu Jianqun <jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\n" + "> From: Xu Jianqun <jay.xu@rock-chips.com>\n" "> \n" "> Add dtsi file for Rockchip rk3399 SoCs, which includes some\n" "> general nodes such as cpu, pmu, cru, gic, amba and so on.\n" @@ -36,7 +18,7 @@ "\n" "please remove any review-cruft like Change-Ids from mainline patches :-)\n" "\n" - "> Signed-off-by: Xu Jianqun <jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\n" + "> Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>\n" "> ---\n" "> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 989\n" "> +++++++++++++++++++++++++++++++ 1 file changed, 989 insertions(+)\n" @@ -157,7 +139,7 @@ "\n" "\n" "> +\n" - "> +\t\tcpu_l0: cpu@0 {\n" + "> +\t\tcpu_l0: cpu at 0 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x0>;\n" @@ -169,7 +151,7 @@ "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu_l1: cpu@1 {\n" + "> +\t\tcpu_l1: cpu at 1 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x1>;\n" @@ -177,7 +159,7 @@ "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu_l2: cpu@2 {\n" + "> +\t\tcpu_l2: cpu at 2 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x2>;\n" @@ -185,7 +167,7 @@ "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu_l3: cpu@3 {\n" + "> +\t\tcpu_l3: cpu at 3 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x3>;\n" @@ -193,7 +175,7 @@ "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu_b0: cpu@100 {\n" + "> +\t\tcpu_b0: cpu at 100 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x100>;\n" @@ -201,7 +183,7 @@ "> +\t\t\tenable-method = \"psci\";\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu_b1: cpu@101 {\n" + "> +\t\tcpu_b1: cpu at 101 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a72\", \"arm,armv8\";\n" "> +\t\t\treg = <0x0 0x101>;\n" @@ -242,7 +224,7 @@ "> +\t\tclock-output-names = \"xin24m\";\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller@fee00000 {\n" + "> +\tgic: interrupt-controller at fee00000 {\n" "> +\t\tcompatible = \"arm,gic-v3\";\n" "> +\t\t#interrupt-cells = <3>;\n" "> +\t\t#address-cells = <2>;\n" @@ -261,7 +243,7 @@ "\n" "again GIC_CPU_MASK_SIMPLE(6)?\n" "\n" - "> +\t\tits: interrupt-controller@fee20000 {\n" + "> +\t\tits: interrupt-controller at fee20000 {\n" "> +\t\t\tcompatible = \"arm,gic-v3-its\";\n" "> +\t\t\tmsi-controller;\n" "> +\t\t\treg = <0x0 0xfee20000 0x0 0x20000>;\n" @@ -274,7 +256,7 @@ "> +\t\t#size-cells = <2>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tdmac_bus: dma-controller@ff6d0000 {\n" + "> +\t\tdmac_bus: dma-controller at ff6d0000 {\n" "> +\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n" "> +\t\t\treg = <0x0 0xff6d0000 0x0 0x4000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -291,10 +273,6 @@ "rest looks nice on first glance :-)\n" "\n" "\n" - "Heiko\n" - "--\n" - "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" - "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" - More majordomo info at http://vger.kernel.org/majordomo-info.html + Heiko -26772f6fa17757ef5df2895bc5e4b29b600546799ecc7dd9d021c79c6bd874e4 +7fccfc75e576b68946be0ea2477ce08523f21e384adcf693e85da92d5f1c79c9
diff --git a/a/1.txt b/N2/1.txt index 7ccbb18..b301e40 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,7 +1,7 @@ Hi Jianqun, Am Mittwoch, 17. Februar 2016, 10:01:16 schrieb jianqun.xu: -> From: Xu Jianqun <jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> +> From: Xu Jianqun <jay.xu@rock-chips.com> > > Add dtsi file for Rockchip rk3399 SoCs, which includes some > general nodes such as cpu, pmu, cru, gic, amba and so on. @@ -10,7 +10,7 @@ Am Mittwoch, 17. Februar 2016, 10:01:16 schrieb jianqun.xu: please remove any review-cruft like Change-Ids from mainline patches :-) -> Signed-off-by: Xu Jianqun <jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org> +> Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com> > --- > arch/arm64/boot/dts/rockchip/rk3399.dtsi | 989 > +++++++++++++++++++++++++++++++ 1 file changed, 989 insertions(+) @@ -266,7 +266,3 @@ rest looks nice on first glance :-) Heiko --- -To unsubscribe from this list: send the line "unsubscribe devicetree" in -the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org -More majordomo info at http://vger.kernel.org/majordomo-info.html diff --git a/a/content_digest b/N2/content_digest index 889ca71..5e12ab7 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,33 +1,32 @@ "ref\01455673992-16469-1-git-send-email-jay.xu@rock-chips.com\0" "ref\01455674476-16655-1-git-send-email-jay.xu@rock-chips.com\0" - "ref\01455674476-16655-1-git-send-email-jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org\0" - "From\0Heiko Stuebner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>\0" + "From\0Heiko Stuebner <heiko@sntech.de>\0" "Subject\0Re: [PATCH 6/6] ARM64: dts: rockchip: add core dtsi file for rk3399\0" "Date\0Wed, 17 Feb 2016 08:00:33 +0100\0" - "To\0jianqun.xu <jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\0" - "Cc\0robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" - pawel.moll-5wv7dgnIgG8@public.gmane.org - mark.rutland-5wv7dgnIgG8@public.gmane.org - ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org - galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - jwerner-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org - broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org - catalin.marinas-5wv7dgnIgG8@public.gmane.org - will.deacon-5wv7dgnIgG8@public.gmane.org - sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - sjoerd.simons-ZGY8ohtN/8pPYcu2f3hruQ@public.gmane.org - huangtao-TNX95d0MmH7DzftRWevZcw@public.gmane.org - linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - " devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\0" + "To\0jianqun.xu <jay.xu@rock-chips.com>\0" + "Cc\0robh+dt@kernel.org" + pawel.moll@arm.com + mark.rutland@arm.com + ijc+devicetree@hellion.org.uk + galak@codeaurora.org + jwerner@chromium.org + broonie@kernel.org + catalin.marinas@arm.com + will.deacon@arm.com + sboyd@codeaurora.org + linus.walleij@linaro.org + sjoerd.simons@collabora.co.uk + huangtao@rock-chips.com + linux-rockchip@lists.infradead.org + linux-kernel@vger.kernel.org + linux-arm-kernel@lists.infradead.org + " devicetree@vger.kernel.org\0" "\00:1\0" "b\0" "Hi Jianqun,\n" "\n" "Am Mittwoch, 17. Februar 2016, 10:01:16 schrieb jianqun.xu:\n" - "> From: Xu Jianqun <jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\n" + "> From: Xu Jianqun <jay.xu@rock-chips.com>\n" "> \n" "> Add dtsi file for Rockchip rk3399 SoCs, which includes some\n" "> general nodes such as cpu, pmu, cru, gic, amba and so on.\n" @@ -36,7 +35,7 @@ "\n" "please remove any review-cruft like Change-Ids from mainline patches :-)\n" "\n" - "> Signed-off-by: Xu Jianqun <jay.xu-TNX95d0MmH7DzftRWevZcw@public.gmane.org>\n" + "> Signed-off-by: Xu Jianqun <jay.xu@rock-chips.com>\n" "> ---\n" "> arch/arm64/boot/dts/rockchip/rk3399.dtsi | 989\n" "> +++++++++++++++++++++++++++++++ 1 file changed, 989 insertions(+)\n" @@ -291,10 +290,6 @@ "rest looks nice on first glance :-)\n" "\n" "\n" - "Heiko\n" - "--\n" - "To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n" - "the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org\n" - More majordomo info at http://vger.kernel.org/majordomo-info.html + Heiko -26772f6fa17757ef5df2895bc5e4b29b600546799ecc7dd9d021c79c6bd874e4 +068f5795c3a353ffcd79c81828d3ea405469e0ed1d98bdb27b7da0701a7c059a
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