* [PATCH 0/2] soc: bcm: brcmstb: Updates to support newer controllers @ 2018-05-11 22:02 ` Florian Fainelli 0 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2018-05-11 22:02 UTC (permalink / raw) To: linux-arm-kernel Hi all, This patch series adds support for newer reveisions of the memory controller which is necessary to make sure we do use the right programming sequence to enter S2 and S3 suspend/resume modes. Doug Berger (1): soc: bcm: brcmstb: pm: Add support for newer rev B3.0 controllers Florian Fainelli (1): soc: bcm: brcmstb: Add missing DDR MEMC compatible strings .../devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 4 ++++ drivers/soc/bcm/brcmstb/pm/pm-arm.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) -- 2.14.1 ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 0/2] soc: bcm: brcmstb: Updates to support newer controllers @ 2018-05-11 22:02 ` Florian Fainelli 0 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2018-05-11 22:02 UTC (permalink / raw) To: linux-arm-kernel Cc: Florian Fainelli, Rob Herring, Mark Rutland, Brian Norris, Gregory Fong, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Doug Berger, Justin Chen, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list Hi all, This patch series adds support for newer reveisions of the memory controller which is necessary to make sure we do use the right programming sequence to enter S2 and S3 suspend/resume modes. Doug Berger (1): soc: bcm: brcmstb: pm: Add support for newer rev B3.0 controllers Florian Fainelli (1): soc: bcm: brcmstb: Add missing DDR MEMC compatible strings .../devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 4 ++++ drivers/soc/bcm/brcmstb/pm/pm-arm.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) -- 2.14.1 ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 0/2] soc: bcm: brcmstb: Updates to support newer controllers @ 2018-05-11 22:02 ` Florian Fainelli 0 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2018-05-11 22:02 UTC (permalink / raw) To: linux-arm-kernel Cc: Florian Fainelli, Rob Herring, Mark Rutland, Brian Norris, Gregory Fong, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Doug Berger, Justin Chen, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list Hi all, This patch series adds support for newer reveisions of the memory controller which is necessary to make sure we do use the right programming sequence to enter S2 and S3 suspend/resume modes. Doug Berger (1): soc: bcm: brcmstb: pm: Add support for newer rev B3.0 controllers Florian Fainelli (1): soc: bcm: brcmstb: Add missing DDR MEMC compatible strings .../devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 4 ++++ drivers/soc/bcm/brcmstb/pm/pm-arm.c | 16 ++++++++++++++++ 2 files changed, 20 insertions(+) -- 2.14.1 ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 1/2] soc: bcm: brcmstb: pm: Add support for newer rev B3.0 controllers 2018-05-11 22:02 ` Florian Fainelli (?) @ 2018-05-11 22:02 ` Florian Fainelli -1 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2018-05-11 22:02 UTC (permalink / raw) To: linux-arm-kernel From: Doug Berger <opendmb@gmail.com> Update the Device Tree binding document and add a matching entry for the MEMC DDR controller revision B3.0 which is found on chips like 7278A0 and newer. Signed-off-by: Doug Berger <opendmb@gmail.com> [florian: tweak commit message, make it apply to upstream kernel] Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 1 + drivers/soc/bcm/brcmstb/pm/pm-arm.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt index c052caad36e8..fb762059e68e 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt @@ -190,6 +190,7 @@ Power-Down (SRPD), among other things. Required properties: - compatible : should contain one of these "brcm,brcmstb-memc-ddr-rev-b.2.2" + "brcm,brcmstb-memc-ddr-rev-b.3.0" "brcm,brcmstb-memc-ddr" - reg : the MEMC DDR register range diff --git a/drivers/soc/bcm/brcmstb/pm/pm-arm.c b/drivers/soc/bcm/brcmstb/pm/pm-arm.c index dcf8c8065508..ade724677238 100644 --- a/drivers/soc/bcm/brcmstb/pm/pm-arm.c +++ b/drivers/soc/bcm/brcmstb/pm/pm-arm.c @@ -631,6 +631,10 @@ static const struct of_device_id brcmstb_memc_of_match[] = { .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2", .data = &ddr_seq_b22, }, + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0", + .data = &ddr_seq_b22, + }, { .compatible = "brcm,brcmstb-memc-ddr", .data = &ddr_seq, -- 2.14.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 1/2] soc: bcm: brcmstb: pm: Add support for newer rev B3.0 controllers @ 2018-05-11 22:02 ` Florian Fainelli 0 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2018-05-11 22:02 UTC (permalink / raw) To: linux-arm-kernel Cc: Doug Berger, Florian Fainelli, Rob Herring, Mark Rutland, Brian Norris, Gregory Fong, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Justin Chen, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list From: Doug Berger <opendmb@gmail.com> Update the Device Tree binding document and add a matching entry for the MEMC DDR controller revision B3.0 which is found on chips like 7278A0 and newer. Signed-off-by: Doug Berger <opendmb@gmail.com> [florian: tweak commit message, make it apply to upstream kernel] Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 1 + drivers/soc/bcm/brcmstb/pm/pm-arm.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt index c052caad36e8..fb762059e68e 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt @@ -190,6 +190,7 @@ Power-Down (SRPD), among other things. Required properties: - compatible : should contain one of these "brcm,brcmstb-memc-ddr-rev-b.2.2" + "brcm,brcmstb-memc-ddr-rev-b.3.0" "brcm,brcmstb-memc-ddr" - reg : the MEMC DDR register range diff --git a/drivers/soc/bcm/brcmstb/pm/pm-arm.c b/drivers/soc/bcm/brcmstb/pm/pm-arm.c index dcf8c8065508..ade724677238 100644 --- a/drivers/soc/bcm/brcmstb/pm/pm-arm.c +++ b/drivers/soc/bcm/brcmstb/pm/pm-arm.c @@ -631,6 +631,10 @@ static const struct of_device_id brcmstb_memc_of_match[] = { .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2", .data = &ddr_seq_b22, }, + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0", + .data = &ddr_seq_b22, + }, { .compatible = "brcm,brcmstb-memc-ddr", .data = &ddr_seq, -- 2.14.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 1/2] soc: bcm: brcmstb: pm: Add support for newer rev B3.0 controllers @ 2018-05-11 22:02 ` Florian Fainelli 0 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2018-05-11 22:02 UTC (permalink / raw) To: linux-arm-kernel Cc: Doug Berger, Florian Fainelli, Rob Herring, Mark Rutland, Brian Norris, Gregory Fong, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Justin Chen, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list From: Doug Berger <opendmb@gmail.com> Update the Device Tree binding document and add a matching entry for the MEMC DDR controller revision B3.0 which is found on chips like 7278A0 and newer. Signed-off-by: Doug Berger <opendmb@gmail.com> [florian: tweak commit message, make it apply to upstream kernel] Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 1 + drivers/soc/bcm/brcmstb/pm/pm-arm.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt index c052caad36e8..fb762059e68e 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt @@ -190,6 +190,7 @@ Power-Down (SRPD), among other things. Required properties: - compatible : should contain one of these "brcm,brcmstb-memc-ddr-rev-b.2.2" + "brcm,brcmstb-memc-ddr-rev-b.3.0" "brcm,brcmstb-memc-ddr" - reg : the MEMC DDR register range diff --git a/drivers/soc/bcm/brcmstb/pm/pm-arm.c b/drivers/soc/bcm/brcmstb/pm/pm-arm.c index dcf8c8065508..ade724677238 100644 --- a/drivers/soc/bcm/brcmstb/pm/pm-arm.c +++ b/drivers/soc/bcm/brcmstb/pm/pm-arm.c @@ -631,6 +631,10 @@ static const struct of_device_id brcmstb_memc_of_match[] = { .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2", .data = &ddr_seq_b22, }, + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0", + .data = &ddr_seq_b22, + }, { .compatible = "brcm,brcmstb-memc-ddr", .data = &ddr_seq, -- 2.14.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 1/2] soc: bcm: brcmstb: pm: Add support for newer rev B3.0 controllers 2018-05-11 22:02 ` Florian Fainelli @ 2018-05-22 22:30 ` Rob Herring -1 siblings, 0 replies; 19+ messages in thread From: Rob Herring @ 2018-05-22 22:30 UTC (permalink / raw) To: linux-arm-kernel On Fri, May 11, 2018 at 03:02:41PM -0700, Florian Fainelli wrote: > From: Doug Berger <opendmb@gmail.com> > > Update the Device Tree binding document and add a matching entry for the > MEMC DDR controller revision B3.0 which is found on chips like 7278A0 > and newer. > > Signed-off-by: Doug Berger <opendmb@gmail.com> > [florian: tweak commit message, make it apply to upstream kernel] > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- > Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 1 + > drivers/soc/bcm/brcmstb/pm/pm-arm.c | 4 ++++ > 2 files changed, 5 insertions(+) Reviewed-by: Rob Herring <robh@kernel.org> Side note: this should really move out of bindings/arm/ to bindings/memory-controllers/ or at least to its own file. Rob ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/2] soc: bcm: brcmstb: pm: Add support for newer rev B3.0 controllers @ 2018-05-22 22:30 ` Rob Herring 0 siblings, 0 replies; 19+ messages in thread From: Rob Herring @ 2018-05-22 22:30 UTC (permalink / raw) To: Florian Fainelli Cc: linux-arm-kernel, Doug Berger, Mark Rutland, Brian Norris, Gregory Fong, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Justin Chen, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list On Fri, May 11, 2018 at 03:02:41PM -0700, Florian Fainelli wrote: > From: Doug Berger <opendmb@gmail.com> > > Update the Device Tree binding document and add a matching entry for the > MEMC DDR controller revision B3.0 which is found on chips like 7278A0 > and newer. > > Signed-off-by: Doug Berger <opendmb@gmail.com> > [florian: tweak commit message, make it apply to upstream kernel] > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- > Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 1 + > drivers/soc/bcm/brcmstb/pm/pm-arm.c | 4 ++++ > 2 files changed, 5 insertions(+) Reviewed-by: Rob Herring <robh@kernel.org> Side note: this should really move out of bindings/arm/ to bindings/memory-controllers/ or at least to its own file. Rob ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 1/2] soc: bcm: brcmstb: pm: Add support for newer rev B3.0 controllers 2018-05-22 22:30 ` Rob Herring @ 2018-06-04 21:16 ` Florian Fainelli -1 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2018-06-04 21:16 UTC (permalink / raw) To: linux-arm-kernel On 05/22/2018 03:30 PM, Rob Herring wrote: > On Fri, May 11, 2018 at 03:02:41PM -0700, Florian Fainelli wrote: >> From: Doug Berger <opendmb@gmail.com> >> >> Update the Device Tree binding document and add a matching entry for the >> MEMC DDR controller revision B3.0 which is found on chips like 7278A0 >> and newer. >> >> Signed-off-by: Doug Berger <opendmb@gmail.com> >> [florian: tweak commit message, make it apply to upstream kernel] >> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> >> --- >> Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 1 + >> drivers/soc/bcm/brcmstb/pm/pm-arm.c | 4 ++++ >> 2 files changed, 5 insertions(+) > > Reviewed-by: Rob Herring <robh@kernel.org> > > Side note: this should really move out of bindings/arm/ to > bindings/memory-controllers/ or at least to its own file. Good idea, thanks, will do that. -- -- Florian ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/2] soc: bcm: brcmstb: pm: Add support for newer rev B3.0 controllers @ 2018-06-04 21:16 ` Florian Fainelli 0 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2018-06-04 21:16 UTC (permalink / raw) To: Rob Herring, Florian Fainelli Cc: linux-arm-kernel, Doug Berger, Mark Rutland, Brian Norris, Gregory Fong, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Justin Chen, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list On 05/22/2018 03:30 PM, Rob Herring wrote: > On Fri, May 11, 2018 at 03:02:41PM -0700, Florian Fainelli wrote: >> From: Doug Berger <opendmb@gmail.com> >> >> Update the Device Tree binding document and add a matching entry for the >> MEMC DDR controller revision B3.0 which is found on chips like 7278A0 >> and newer. >> >> Signed-off-by: Doug Berger <opendmb@gmail.com> >> [florian: tweak commit message, make it apply to upstream kernel] >> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> >> --- >> Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 1 + >> drivers/soc/bcm/brcmstb/pm/pm-arm.c | 4 ++++ >> 2 files changed, 5 insertions(+) > > Reviewed-by: Rob Herring <robh@kernel.org> > > Side note: this should really move out of bindings/arm/ to > bindings/memory-controllers/ or at least to its own file. Good idea, thanks, will do that. -- -- Florian ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 1/2] soc: bcm: brcmstb: pm: Add support for newer rev B3.0 controllers 2018-05-11 22:02 ` Florian Fainelli @ 2018-06-04 21:15 ` Florian Fainelli -1 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2018-06-04 21:15 UTC (permalink / raw) To: linux-arm-kernel On Fri, 11 May 2018 15:02:41 -0700, Florian Fainelli <f.fainelli@gmail.com> wrote: > From: Doug Berger <opendmb@gmail.com> > > Update the Device Tree binding document and add a matching entry for the > MEMC DDR controller revision B3.0 which is found on chips like 7278A0 > and newer. > > Signed-off-by: Doug Berger <opendmb@gmail.com> > [florian: tweak commit message, make it apply to upstream kernel] > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- Applied to drivers/next, thanks! -- Florian ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/2] soc: bcm: brcmstb: pm: Add support for newer rev B3.0 controllers @ 2018-06-04 21:15 ` Florian Fainelli 0 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2018-06-04 21:15 UTC (permalink / raw) To: bcm-kernel-feedback-list, linux-arm-kernel Cc: Doug Berger, Rob Herring, Mark Rutland, Brian Norris, Gregory Fong, Justin Chen, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list On Fri, 11 May 2018 15:02:41 -0700, Florian Fainelli <f.fainelli@gmail.com> wrote: > From: Doug Berger <opendmb@gmail.com> > > Update the Device Tree binding document and add a matching entry for the > MEMC DDR controller revision B3.0 which is found on chips like 7278A0 > and newer. > > Signed-off-by: Doug Berger <opendmb@gmail.com> > [florian: tweak commit message, make it apply to upstream kernel] > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- Applied to drivers/next, thanks! -- Florian ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 2/2] soc: bcm: brcmstb: Add missing DDR MEMC compatible strings 2018-05-11 22:02 ` Florian Fainelli (?) @ 2018-05-11 22:02 ` Florian Fainelli -1 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2018-05-11 22:02 UTC (permalink / raw) To: linux-arm-kernel We would not be matching the following chip/compatible strings combinations, which would lead to not setting the warm boot flag correctly, fix that: 7260A0/B0: brcm,brcmstb-memc-ddr-rev-b.2.1 7255A0: brcm,brcmstb-memc-ddr-rev-b.2.3 7278Bx: brcm,brcmstb-memc-ddr-rev-b.3.1 The B2.1 core (which is in 7260 A0 and B0) doesn't have the SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL setup in the memsys init code, nor does it have the warm boot flag re-definition on entry. Those changes were for B2.2 and later MEMSYS cores. Fall back to the previous S2/S3 entry method for these specific chips. Fixes: 0b741b8234c8 ("soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 3 +++ drivers/soc/bcm/brcmstb/pm/pm-arm.c | 12 ++++++++++++ 2 files changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt index fb762059e68e..104cc9b41df4 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt @@ -189,8 +189,11 @@ Power-Down (SRPD), among other things. Required properties: - compatible : should contain one of these + "brcm,brcmstb-memc-ddr-rev-b.2.1" "brcm,brcmstb-memc-ddr-rev-b.2.2" + "brcm,brcmstb-memc-ddr-rev-b.2.3" "brcm,brcmstb-memc-ddr-rev-b.3.0" + "brcm,brcmstb-memc-ddr-rev-b.3.1" "brcm,brcmstb-memc-ddr" - reg : the MEMC DDR register range diff --git a/drivers/soc/bcm/brcmstb/pm/pm-arm.c b/drivers/soc/bcm/brcmstb/pm/pm-arm.c index ade724677238..a5577dd5eb08 100644 --- a/drivers/soc/bcm/brcmstb/pm/pm-arm.c +++ b/drivers/soc/bcm/brcmstb/pm/pm-arm.c @@ -627,14 +627,26 @@ static const struct of_device_id ddr_shimphy_dt_ids[] = { }; static const struct of_device_id brcmstb_memc_of_match[] = { + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1", + .data = &ddr_seq, + }, { .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2", .data = &ddr_seq_b22, }, + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3", + .data = &ddr_seq_b22, + }, { .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0", .data = &ddr_seq_b22, }, + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1", + .data = &ddr_seq_b22, + }, { .compatible = "brcm,brcmstb-memc-ddr", .data = &ddr_seq, -- 2.14.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 2/2] soc: bcm: brcmstb: Add missing DDR MEMC compatible strings @ 2018-05-11 22:02 ` Florian Fainelli 0 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2018-05-11 22:02 UTC (permalink / raw) To: linux-arm-kernel Cc: Florian Fainelli, Rob Herring, Mark Rutland, Brian Norris, Gregory Fong, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Doug Berger, Justin Chen, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list We would not be matching the following chip/compatible strings combinations, which would lead to not setting the warm boot flag correctly, fix that: 7260A0/B0: brcm,brcmstb-memc-ddr-rev-b.2.1 7255A0: brcm,brcmstb-memc-ddr-rev-b.2.3 7278Bx: brcm,brcmstb-memc-ddr-rev-b.3.1 The B2.1 core (which is in 7260 A0 and B0) doesn't have the SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL setup in the memsys init code, nor does it have the warm boot flag re-definition on entry. Those changes were for B2.2 and later MEMSYS cores. Fall back to the previous S2/S3 entry method for these specific chips. Fixes: 0b741b8234c8 ("soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 3 +++ drivers/soc/bcm/brcmstb/pm/pm-arm.c | 12 ++++++++++++ 2 files changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt index fb762059e68e..104cc9b41df4 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt @@ -189,8 +189,11 @@ Power-Down (SRPD), among other things. Required properties: - compatible : should contain one of these + "brcm,brcmstb-memc-ddr-rev-b.2.1" "brcm,brcmstb-memc-ddr-rev-b.2.2" + "brcm,brcmstb-memc-ddr-rev-b.2.3" "brcm,brcmstb-memc-ddr-rev-b.3.0" + "brcm,brcmstb-memc-ddr-rev-b.3.1" "brcm,brcmstb-memc-ddr" - reg : the MEMC DDR register range diff --git a/drivers/soc/bcm/brcmstb/pm/pm-arm.c b/drivers/soc/bcm/brcmstb/pm/pm-arm.c index ade724677238..a5577dd5eb08 100644 --- a/drivers/soc/bcm/brcmstb/pm/pm-arm.c +++ b/drivers/soc/bcm/brcmstb/pm/pm-arm.c @@ -627,14 +627,26 @@ static const struct of_device_id ddr_shimphy_dt_ids[] = { }; static const struct of_device_id brcmstb_memc_of_match[] = { + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1", + .data = &ddr_seq, + }, { .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2", .data = &ddr_seq_b22, }, + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3", + .data = &ddr_seq_b22, + }, { .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0", .data = &ddr_seq_b22, }, + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1", + .data = &ddr_seq_b22, + }, { .compatible = "brcm,brcmstb-memc-ddr", .data = &ddr_seq, -- 2.14.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 2/2] soc: bcm: brcmstb: Add missing DDR MEMC compatible strings @ 2018-05-11 22:02 ` Florian Fainelli 0 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2018-05-11 22:02 UTC (permalink / raw) To: linux-arm-kernel Cc: Florian Fainelli, Rob Herring, Mark Rutland, Brian Norris, Gregory Fong, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Doug Berger, Justin Chen, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list We would not be matching the following chip/compatible strings combinations, which would lead to not setting the warm boot flag correctly, fix that: 7260A0/B0: brcm,brcmstb-memc-ddr-rev-b.2.1 7255A0: brcm,brcmstb-memc-ddr-rev-b.2.3 7278Bx: brcm,brcmstb-memc-ddr-rev-b.3.1 The B2.1 core (which is in 7260 A0 and B0) doesn't have the SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL setup in the memsys init code, nor does it have the warm boot flag re-definition on entry. Those changes were for B2.2 and later MEMSYS cores. Fall back to the previous S2/S3 entry method for these specific chips. Fixes: 0b741b8234c8 ("soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> --- Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 3 +++ drivers/soc/bcm/brcmstb/pm/pm-arm.c | 12 ++++++++++++ 2 files changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt index fb762059e68e..104cc9b41df4 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt @@ -189,8 +189,11 @@ Power-Down (SRPD), among other things. Required properties: - compatible : should contain one of these + "brcm,brcmstb-memc-ddr-rev-b.2.1" "brcm,brcmstb-memc-ddr-rev-b.2.2" + "brcm,brcmstb-memc-ddr-rev-b.2.3" "brcm,brcmstb-memc-ddr-rev-b.3.0" + "brcm,brcmstb-memc-ddr-rev-b.3.1" "brcm,brcmstb-memc-ddr" - reg : the MEMC DDR register range diff --git a/drivers/soc/bcm/brcmstb/pm/pm-arm.c b/drivers/soc/bcm/brcmstb/pm/pm-arm.c index ade724677238..a5577dd5eb08 100644 --- a/drivers/soc/bcm/brcmstb/pm/pm-arm.c +++ b/drivers/soc/bcm/brcmstb/pm/pm-arm.c @@ -627,14 +627,26 @@ static const struct of_device_id ddr_shimphy_dt_ids[] = { }; static const struct of_device_id brcmstb_memc_of_match[] = { + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.1", + .data = &ddr_seq, + }, { .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.2", .data = &ddr_seq_b22, }, + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.2.3", + .data = &ddr_seq_b22, + }, { .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.0", .data = &ddr_seq_b22, }, + { + .compatible = "brcm,brcmstb-memc-ddr-rev-b.3.1", + .data = &ddr_seq_b22, + }, { .compatible = "brcm,brcmstb-memc-ddr", .data = &ddr_seq, -- 2.14.1 ^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 2/2] soc: bcm: brcmstb: Add missing DDR MEMC compatible strings 2018-05-11 22:02 ` Florian Fainelli @ 2018-05-22 22:31 ` Rob Herring -1 siblings, 0 replies; 19+ messages in thread From: Rob Herring @ 2018-05-22 22:31 UTC (permalink / raw) To: linux-arm-kernel On Fri, May 11, 2018 at 03:02:42PM -0700, Florian Fainelli wrote: > We would not be matching the following chip/compatible strings > combinations, which would lead to not setting the warm boot flag > correctly, fix that: > > 7260A0/B0: brcm,brcmstb-memc-ddr-rev-b.2.1 > 7255A0: brcm,brcmstb-memc-ddr-rev-b.2.3 > 7278Bx: brcm,brcmstb-memc-ddr-rev-b.3.1 > > The B2.1 core (which is in 7260 A0 and B0) doesn't have the > SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL setup in the memsys init code, nor > does it have the warm boot flag re-definition on entry. Those changes > were for B2.2 and later MEMSYS cores. Fall back to the previous S2/S3 > entry method for these specific chips. > > Fixes: 0b741b8234c8 ("soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)") > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- > Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 3 +++ > drivers/soc/bcm/brcmstb/pm/pm-arm.c | 12 ++++++++++++ > 2 files changed, 15 insertions(+) Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/2] soc: bcm: brcmstb: Add missing DDR MEMC compatible strings @ 2018-05-22 22:31 ` Rob Herring 0 siblings, 0 replies; 19+ messages in thread From: Rob Herring @ 2018-05-22 22:31 UTC (permalink / raw) To: Florian Fainelli Cc: linux-arm-kernel, Mark Rutland, Brian Norris, Gregory Fong, maintainer:BROADCOM BCM7XXX ARM ARCHITECTURE, Doug Berger, Justin Chen, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list On Fri, May 11, 2018 at 03:02:42PM -0700, Florian Fainelli wrote: > We would not be matching the following chip/compatible strings > combinations, which would lead to not setting the warm boot flag > correctly, fix that: > > 7260A0/B0: brcm,brcmstb-memc-ddr-rev-b.2.1 > 7255A0: brcm,brcmstb-memc-ddr-rev-b.2.3 > 7278Bx: brcm,brcmstb-memc-ddr-rev-b.3.1 > > The B2.1 core (which is in 7260 A0 and B0) doesn't have the > SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL setup in the memsys init code, nor > does it have the warm boot flag re-definition on entry. Those changes > were for B2.2 and later MEMSYS cores. Fall back to the previous S2/S3 > entry method for these specific chips. > > Fixes: 0b741b8234c8 ("soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)") > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- > Documentation/devicetree/bindings/arm/bcm/brcm,brcmstb.txt | 3 +++ > drivers/soc/bcm/brcmstb/pm/pm-arm.c | 12 ++++++++++++ > 2 files changed, 15 insertions(+) Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 2/2] soc: bcm: brcmstb: Add missing DDR MEMC compatible strings 2018-05-11 22:02 ` Florian Fainelli @ 2018-06-04 21:15 ` Florian Fainelli -1 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2018-06-04 21:15 UTC (permalink / raw) To: linux-arm-kernel On Fri, 11 May 2018 15:02:42 -0700, Florian Fainelli <f.fainelli@gmail.com> wrote: > We would not be matching the following chip/compatible strings > combinations, which would lead to not setting the warm boot flag > correctly, fix that: > > 7260A0/B0: brcm,brcmstb-memc-ddr-rev-b.2.1 > 7255A0: brcm,brcmstb-memc-ddr-rev-b.2.3 > 7278Bx: brcm,brcmstb-memc-ddr-rev-b.3.1 > > The B2.1 core (which is in 7260 A0 and B0) doesn't have the > SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL setup in the memsys init code, nor > does it have the warm boot flag re-definition on entry. Those changes > were for B2.2 and later MEMSYS cores. Fall back to the previous S2/S3 > entry method for these specific chips. > > Fixes: 0b741b8234c8 ("soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)") > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- Applied to drivers/next, thanks! -- Florian ^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 2/2] soc: bcm: brcmstb: Add missing DDR MEMC compatible strings @ 2018-06-04 21:15 ` Florian Fainelli 0 siblings, 0 replies; 19+ messages in thread From: Florian Fainelli @ 2018-06-04 21:15 UTC (permalink / raw) To: bcm-kernel-feedback-list, linux-arm-kernel Cc: Rob Herring, Mark Rutland, Brian Norris, Gregory Fong, Doug Berger, Justin Chen, open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, open list On Fri, 11 May 2018 15:02:42 -0700, Florian Fainelli <f.fainelli@gmail.com> wrote: > We would not be matching the following chip/compatible strings > combinations, which would lead to not setting the warm boot flag > correctly, fix that: > > 7260A0/B0: brcm,brcmstb-memc-ddr-rev-b.2.1 > 7255A0: brcm,brcmstb-memc-ddr-rev-b.2.3 > 7278Bx: brcm,brcmstb-memc-ddr-rev-b.3.1 > > The B2.1 core (which is in 7260 A0 and B0) doesn't have the > SHIMPHY_ADDR_CNTL_0_DDR_PAD_CNTRL setup in the memsys init code, nor > does it have the warm boot flag re-definition on entry. Those changes > were for B2.2 and later MEMSYS cores. Fall back to the previous S2/S3 > entry method for these specific chips. > > Fixes: 0b741b8234c8 ("soc: bcm: brcmstb: Add support for S2/S3/S5 suspend states (ARM)") > Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> > --- Applied to drivers/next, thanks! -- Florian ^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2018-06-04 21:16 UTC | newest] Thread overview: 19+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2018-05-11 22:02 [PATCH 0/2] soc: bcm: brcmstb: Updates to support newer controllers Florian Fainelli 2018-05-11 22:02 ` Florian Fainelli 2018-05-11 22:02 ` Florian Fainelli 2018-05-11 22:02 ` [PATCH 1/2] soc: bcm: brcmstb: pm: Add support for newer rev B3.0 controllers Florian Fainelli 2018-05-11 22:02 ` Florian Fainelli 2018-05-11 22:02 ` Florian Fainelli 2018-05-22 22:30 ` Rob Herring 2018-05-22 22:30 ` Rob Herring 2018-06-04 21:16 ` Florian Fainelli 2018-06-04 21:16 ` Florian Fainelli 2018-06-04 21:15 ` Florian Fainelli 2018-06-04 21:15 ` Florian Fainelli 2018-05-11 22:02 ` [PATCH 2/2] soc: bcm: brcmstb: Add missing DDR MEMC compatible strings Florian Fainelli 2018-05-11 22:02 ` Florian Fainelli 2018-05-11 22:02 ` Florian Fainelli 2018-05-22 22:31 ` Rob Herring 2018-05-22 22:31 ` Rob Herring 2018-06-04 21:15 ` Florian Fainelli 2018-06-04 21:15 ` Florian Fainelli
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.