From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from perceval.ideasonboard.com ([213.167.242.64]:38192 "EHLO perceval.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726010AbeHTMmE (ORCPT ); Mon, 20 Aug 2018 08:42:04 -0400 From: Laurent Pinchart To: Ulrich Hecht Cc: linux-renesas-soc@vger.kernel.org, dri-devel@lists.freedesktop.org, jacopo+renesas@jmondi.org, kieran.bingham+renesas@ideasonboard.com, Koji Matsuoka Subject: Re: [PROTO][PATCH 05/10] drm/bridge: adv7511: Add max-clock, min-vrefresh options Date: Mon, 20 Aug 2018 12:28:06 +0300 Message-ID: <2454542.vJvYSti9iT@avalon> In-Reply-To: <1534254604-24204-6-git-send-email-uli+renesas@fpond.eu> References: <1534254604-24204-1-git-send-email-uli+renesas@fpond.eu> <1534254604-24204-6-git-send-email-uli+renesas@fpond.eu> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-renesas-soc-owner@vger.kernel.org List-ID: Hi Ulrich, Thank you for the patch. On Tuesday, 14 August 2018 16:49:59 EEST Ulrich Hecht wrote: > From: Koji Matsuoka > > This patch adds the option to specify a maximal clock and a minimal vertical > refresh rate. What is this needed for ? > Signed-off-by: Koji Matsuoka > [uli: renamed properties, fixed transposed parsing] > Signed-off-by: Ulrich Hecht > --- > drivers/gpu/drm/bridge/adv7511/adv7511.h | 7 +++++++ > drivers/gpu/drm/bridge/adv7511/adv7511_drv.c | 22 ++++++++++++++++++++++ You're missing updates to the DT bindings. > 2 files changed, 29 insertions(+) > > diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511.h > b/drivers/gpu/drm/bridge/adv7511/adv7511.h index 73d8ccb..7f29d4f 100644 > --- a/drivers/gpu/drm/bridge/adv7511/adv7511.h > +++ b/drivers/gpu/drm/bridge/adv7511/adv7511.h > @@ -271,6 +271,8 @@ enum adv7511_sync_polarity { > * @sync_pulse: Select the sync pulse > * @vsync_polarity: vsync input signal configuration > * @hsync_polarity: hsync input signal configuration > + * @min_vrefresh_option: min vrefresh option > + * @max_freq_option: max frequency option > */ > struct adv7511_link_config { > unsigned int input_color_depth; > @@ -285,6 +287,9 @@ struct adv7511_link_config { > enum adv7511_input_sync_pulse sync_pulse; > enum adv7511_sync_polarity vsync_polarity; > enum adv7511_sync_polarity hsync_polarity; > + > + unsigned int min_vrefresh_option; > + unsigned int max_freq_option; > }; > > /** > @@ -354,6 +359,8 @@ struct adv7511 { > enum adv7511_sync_polarity vsync_polarity; > enum adv7511_sync_polarity hsync_polarity; > bool rgb; > + unsigned int min_vref; > + unsigned int max_freq; > > struct gpio_desc *gpio_pd; > > diff --git a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c > b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c index 6437b87..2938b02 > 100644 > --- a/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c > +++ b/drivers/gpu/drm/bridge/adv7511/adv7511_drv.c > @@ -323,6 +323,8 @@ static void adv7511_set_link_config(struct adv7511 > *adv7511, adv7511->hsync_polarity = config->hsync_polarity; > adv7511->vsync_polarity = config->vsync_polarity; > adv7511->rgb = config->input_colorspace == HDMI_COLORSPACE_RGB; > + adv7511->min_vref = config->min_vrefresh_option; > + adv7511->max_freq = config->max_freq_option; > } > > static void __adv7511_power_on(struct adv7511 *adv7511) > @@ -660,6 +662,16 @@ static enum drm_mode_status adv7511_mode_valid(struct > adv7511 *adv7511, if (mode->clock > 165000) > return MODE_CLOCK_HIGH; > > + if (adv7511->max_freq) { > + if (mode->clock > (adv7511->max_freq / 1000)) > + return MODE_CLOCK_HIGH; > + } > + > + if (adv7511->min_vref) { > + if (drm_mode_vrefresh(mode) < adv7511->min_vref) > + return MODE_BAD; > + } > + > return MODE_OK; > } > > @@ -1074,6 +1086,16 @@ static int adv7511_parse_dt(struct device_node *np, > config->vsync_polarity = ADV7511_SYNC_POLARITY_PASSTHROUGH; > config->hsync_polarity = ADV7511_SYNC_POLARITY_PASSTHROUGH; > > + ret = of_property_read_u32(np, "max-clock", > + &config->max_freq_option); > + if (ret < 0) > + config->max_freq_option = 0; > + > + ret = of_property_read_u32(np, "min-vrefresh", > + &config->min_vrefresh_option); > + if (ret < 0) > + config->min_vrefresh_option = 0; > + > return 0; > } -- Regards, Laurent Pinchart From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laurent Pinchart Subject: Re: [PROTO][PATCH 05/10] drm/bridge: adv7511: Add max-clock, min-vrefresh options Date: Mon, 20 Aug 2018 12:28:06 +0300 Message-ID: <2454542.vJvYSti9iT@avalon> References: <1534254604-24204-1-git-send-email-uli+renesas@fpond.eu> <1534254604-24204-6-git-send-email-uli+renesas@fpond.eu> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from perceval.ideasonboard.com (perceval.ideasonboard.com [IPv6:2001:4b98:dc2:55:216:3eff:fef7:d647]) by gabe.freedesktop.org (Postfix) with ESMTPS id 988E689E0C for ; Mon, 20 Aug 2018 09:27:12 +0000 (UTC) In-Reply-To: <1534254604-24204-6-git-send-email-uli+renesas@fpond.eu> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: Ulrich Hecht Cc: linux-renesas-soc@vger.kernel.org, kieran.bingham+renesas@ideasonboard.com, jacopo+renesas@jmondi.org, Koji Matsuoka , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org SGkgVWxyaWNoLAoKVGhhbmsgeW91IGZvciB0aGUgcGF0Y2guCgpPbiBUdWVzZGF5LCAxNCBBdWd1 c3QgMjAxOCAxNjo0OTo1OSBFRVNUIFVscmljaCBIZWNodCB3cm90ZToKPiBGcm9tOiBLb2ppIE1h dHN1b2thIDxrb2ppLm1hdHN1b2thLnhtQHJlbmVzYXMuY29tPgo+IAo+IFRoaXMgcGF0Y2ggYWRk cyB0aGUgb3B0aW9uIHRvIHNwZWNpZnkgYSBtYXhpbWFsIGNsb2NrIGFuZCBhIG1pbmltYWwgdmVy dGljYWwKPiByZWZyZXNoIHJhdGUuCgpXaGF0IGlzIHRoaXMgbmVlZGVkIGZvciA/Cgo+IFNpZ25l ZC1vZmYtYnk6IEtvamkgTWF0c3Vva2EgPGtvamkubWF0c3Vva2EueG1AcmVuZXNhcy5jb20+Cj4g W3VsaTogcmVuYW1lZCBwcm9wZXJ0aWVzLCBmaXhlZCB0cmFuc3Bvc2VkIHBhcnNpbmddCj4gU2ln bmVkLW9mZi1ieTogVWxyaWNoIEhlY2h0IDx1bGkrcmVuZXNhc0BmcG9uZC5ldT4KPiAtLS0KPiAg ZHJpdmVycy9ncHUvZHJtL2JyaWRnZS9hZHY3NTExL2Fkdjc1MTEuaCAgICAgfCAgNyArKysrKysr Cj4gIGRyaXZlcnMvZ3B1L2RybS9icmlkZ2UvYWR2NzUxMS9hZHY3NTExX2Rydi5jIHwgMjIgKysr KysrKysrKysrKysrKysrKysrKwoKWW91J3JlIG1pc3NpbmcgdXBkYXRlcyB0byB0aGUgRFQgYmlu ZGluZ3MuCgo+ICAyIGZpbGVzIGNoYW5nZWQsIDI5IGluc2VydGlvbnMoKykKPiAKPiBkaWZmIC0t Z2l0IGEvZHJpdmVycy9ncHUvZHJtL2JyaWRnZS9hZHY3NTExL2Fkdjc1MTEuaAo+IGIvZHJpdmVy cy9ncHUvZHJtL2JyaWRnZS9hZHY3NTExL2Fkdjc1MTEuaCBpbmRleCA3M2Q4Y2NiLi43ZjI5ZDRm IDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9icmlkZ2UvYWR2NzUxMS9hZHY3NTExLmgK PiArKysgYi9kcml2ZXJzL2dwdS9kcm0vYnJpZGdlL2Fkdjc1MTEvYWR2NzUxMS5oCj4gQEAgLTI3 MSw2ICsyNzEsOCBAQCBlbnVtIGFkdjc1MTFfc3luY19wb2xhcml0eSB7Cj4gICAqIEBzeW5jX3B1 bHNlOgkJCVNlbGVjdCB0aGUgc3luYyBwdWxzZQo+ICAgKiBAdnN5bmNfcG9sYXJpdHk6CQl2c3lu YyBpbnB1dCBzaWduYWwgY29uZmlndXJhdGlvbgo+ICAgKiBAaHN5bmNfcG9sYXJpdHk6CQloc3lu YyBpbnB1dCBzaWduYWwgY29uZmlndXJhdGlvbgo+ICsgKiBAbWluX3ZyZWZyZXNoX29wdGlvbjoJ bWluIHZyZWZyZXNoIG9wdGlvbgo+ICsgKiBAbWF4X2ZyZXFfb3B0aW9uOgkJbWF4IGZyZXF1ZW5j eSBvcHRpb24KPiAgICovCj4gIHN0cnVjdCBhZHY3NTExX2xpbmtfY29uZmlnIHsKPiAgCXVuc2ln bmVkIGludCBpbnB1dF9jb2xvcl9kZXB0aDsKPiBAQCAtMjg1LDYgKzI4Nyw5IEBAIHN0cnVjdCBh ZHY3NTExX2xpbmtfY29uZmlnIHsKPiAgCWVudW0gYWR2NzUxMV9pbnB1dF9zeW5jX3B1bHNlIHN5 bmNfcHVsc2U7Cj4gIAllbnVtIGFkdjc1MTFfc3luY19wb2xhcml0eSB2c3luY19wb2xhcml0eTsK PiAgCWVudW0gYWR2NzUxMV9zeW5jX3BvbGFyaXR5IGhzeW5jX3BvbGFyaXR5Owo+ICsKPiArCXVu c2lnbmVkIGludCBtaW5fdnJlZnJlc2hfb3B0aW9uOwo+ICsJdW5zaWduZWQgaW50IG1heF9mcmVx X29wdGlvbjsKPiAgfTsKPiAKPiAgLyoqCj4gQEAgLTM1NCw2ICszNTksOCBAQCBzdHJ1Y3QgYWR2 NzUxMSB7Cj4gIAllbnVtIGFkdjc1MTFfc3luY19wb2xhcml0eSB2c3luY19wb2xhcml0eTsKPiAg CWVudW0gYWR2NzUxMV9zeW5jX3BvbGFyaXR5IGhzeW5jX3BvbGFyaXR5Owo+ICAJYm9vbCByZ2I7 Cj4gKwl1bnNpZ25lZCBpbnQgbWluX3ZyZWY7Cj4gKwl1bnNpZ25lZCBpbnQgbWF4X2ZyZXE7Cj4g Cj4gIAlzdHJ1Y3QgZ3Bpb19kZXNjICpncGlvX3BkOwo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJz L2dwdS9kcm0vYnJpZGdlL2Fkdjc1MTEvYWR2NzUxMV9kcnYuYwo+IGIvZHJpdmVycy9ncHUvZHJt L2JyaWRnZS9hZHY3NTExL2Fkdjc1MTFfZHJ2LmMgaW5kZXggNjQzN2I4Ny4uMjkzOGIwMgo+IDEw MDY0NAo+IC0tLSBhL2RyaXZlcnMvZ3B1L2RybS9icmlkZ2UvYWR2NzUxMS9hZHY3NTExX2Rydi5j Cj4gKysrIGIvZHJpdmVycy9ncHUvZHJtL2JyaWRnZS9hZHY3NTExL2Fkdjc1MTFfZHJ2LmMKPiBA QCAtMzIzLDYgKzMyMyw4IEBAIHN0YXRpYyB2b2lkIGFkdjc1MTFfc2V0X2xpbmtfY29uZmlnKHN0 cnVjdCBhZHY3NTExCj4gKmFkdjc1MTEsIGFkdjc1MTEtPmhzeW5jX3BvbGFyaXR5ID0gY29uZmln LT5oc3luY19wb2xhcml0eTsKPiAgCWFkdjc1MTEtPnZzeW5jX3BvbGFyaXR5ID0gY29uZmlnLT52 c3luY19wb2xhcml0eTsKPiAgCWFkdjc1MTEtPnJnYiA9IGNvbmZpZy0+aW5wdXRfY29sb3JzcGFj ZSA9PSBIRE1JX0NPTE9SU1BBQ0VfUkdCOwo+ICsJYWR2NzUxMS0+bWluX3ZyZWYgPSBjb25maWct Pm1pbl92cmVmcmVzaF9vcHRpb247Cj4gKwlhZHY3NTExLT5tYXhfZnJlcSA9IGNvbmZpZy0+bWF4 X2ZyZXFfb3B0aW9uOwo+ICB9Cj4gCj4gIHN0YXRpYyB2b2lkIF9fYWR2NzUxMV9wb3dlcl9vbihz dHJ1Y3QgYWR2NzUxMSAqYWR2NzUxMSkKPiBAQCAtNjYwLDYgKzY2MiwxNiBAQCBzdGF0aWMgZW51 bSBkcm1fbW9kZV9zdGF0dXMgYWR2NzUxMV9tb2RlX3ZhbGlkKHN0cnVjdAo+IGFkdjc1MTEgKmFk djc1MTEsIGlmIChtb2RlLT5jbG9jayA+IDE2NTAwMCkKPiAgCQlyZXR1cm4gTU9ERV9DTE9DS19I SUdIOwo+IAo+ICsJaWYgKGFkdjc1MTEtPm1heF9mcmVxKSB7Cj4gKwkJaWYgKG1vZGUtPmNsb2Nr ID4gKGFkdjc1MTEtPm1heF9mcmVxIC8gMTAwMCkpCj4gKwkJCXJldHVybiBNT0RFX0NMT0NLX0hJ R0g7Cj4gKwl9Cj4gKwo+ICsJaWYgKGFkdjc1MTEtPm1pbl92cmVmKSB7Cj4gKwkJaWYgKGRybV9t b2RlX3ZyZWZyZXNoKG1vZGUpIDwgYWR2NzUxMS0+bWluX3ZyZWYpCj4gKwkJCXJldHVybiBNT0RF X0JBRDsKPiArCX0KPiArCj4gIAlyZXR1cm4gTU9ERV9PSzsKPiAgfQo+IAo+IEBAIC0xMDc0LDYg KzEwODYsMTYgQEAgc3RhdGljIGludCBhZHY3NTExX3BhcnNlX2R0KHN0cnVjdCBkZXZpY2Vfbm9k ZSAqbnAsCj4gIAljb25maWctPnZzeW5jX3BvbGFyaXR5ID0gQURWNzUxMV9TWU5DX1BPTEFSSVRZ X1BBU1NUSFJPVUdIOwo+ICAJY29uZmlnLT5oc3luY19wb2xhcml0eSA9IEFEVjc1MTFfU1lOQ19Q T0xBUklUWV9QQVNTVEhST1VHSDsKPiAKPiArCXJldCA9IG9mX3Byb3BlcnR5X3JlYWRfdTMyKG5w LCAibWF4LWNsb2NrIiwKPiArCQkJCSAgICZjb25maWctPm1heF9mcmVxX29wdGlvbik7Cj4gKwlp ZiAocmV0IDwgMCkKPiArCQljb25maWctPm1heF9mcmVxX29wdGlvbiA9IDA7Cj4gKwo+ICsJcmV0 ID0gb2ZfcHJvcGVydHlfcmVhZF91MzIobnAsICJtaW4tdnJlZnJlc2giLAo+ICsJCQkJICAgJmNv bmZpZy0+bWluX3ZyZWZyZXNoX29wdGlvbik7Cj4gKwlpZiAocmV0IDwgMCkKPiArCQljb25maWct Pm1pbl92cmVmcmVzaF9vcHRpb24gPSAwOwo+ICsKPiAgCXJldHVybiAwOwo+ICB9CgoKLS0gClJl Z2FyZHMsCgpMYXVyZW50IFBpbmNoYXJ0CgoKCl9fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fCmRyaS1kZXZlbCBtYWlsaW5nIGxpc3QKZHJpLWRldmVsQGxpc3Rz LmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xp c3RpbmZvL2RyaS1kZXZlbAo=