diff for duplicates of <24573164.okRNXjvZ1B@phil> diff --git a/a/1.txt b/N1/1.txt index 254c600..6cb4d90 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -92,7 +92,7 @@ As the rk3228 also does not have a pmu, does the newly created "rockchip,rk3036-smp" work for you? > + -> + cpu0: cpu@f00 { +> + cpu0: cpu at f00 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf00>; @@ -105,21 +105,21 @@ As the rk3228 also does not have a pmu, does the newly created > + clocks = <&cru ARMCLK>; > + }; > + -> + cpu1: cpu@f01 { +> + cpu1: cpu at f01 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf01>; > + resets = <&cru SRST_CORE1>; > + }; > + -> + cpu2: cpu@f02 { +> + cpu2: cpu at f02 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf02>; > + resets = <&cru SRST_CORE2>; > + }; > + -> + cpu3: cpu@f03 { +> + cpu3: cpu at f03 { > + device_type = "cpu"; > + compatible = "arm,cortex-a7"; > + reg = <0xf03>; @@ -133,7 +133,7 @@ As the rk3228 also does not have a pmu, does the newly created > + #size-cells = <1>; > + ranges; > + -> + pdma: pdma@110f0000 { +> + pdma: pdma at 110f0000 { > + compatible = "arm,pl330", "arm,primecell"; > + reg = <0x110f0000 0x4000>; > + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, @@ -208,7 +208,7 @@ please. > + #clock-cells = <0>; > + }; > + -> + cru: clock-controller@110e0000 { +> + cru: clock-controller at 110e0000 { > + compatible = "rockchip,rk3228-cru"; > + reg = <0x110e0000 0x1000>; > + rockchip,grf = <&grf>; @@ -218,7 +218,7 @@ please. > + assigned-clock-rates = <594000000>; > + }; > + -> + gic: interrupt-controller@32010000 { +> + gic: interrupt-controller at 32010000 { please order by register address, so gic should move quite a bit lower. @@ -236,12 +236,12 @@ please also provide the vgic registers and interrupt. > + }; > + -> + grf: syscon@11000000 { +> + grf: syscon at 11000000 { > + compatible = "syscon"; > + reg = <0x11000000 0x1000>; > + }; > + -> + timer: timer@110c0000 { +> + timer: timer at 110c0000 { > + compatible = "rockchip,rk3288-timer"; > + reg = <0x110c0000 0x20>; > + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; @@ -249,7 +249,7 @@ please also provide the vgic registers and interrupt. > + clock-names = "timer", "pclk"; > + }; > + -> + emmc: dwmmc@30020000 { +> + emmc: dwmmc at 30020000 { > + compatible = "rockchip,rk3288-dw-mshc"; > + clock-frequency = <37500000>; > + clock-freq-min-max = <400000 37500000>; @@ -278,7 +278,7 @@ the controller. > + status = "disabled"; > + }; > + -> + pwm0: pwm@110b0000 { +> + pwm0: pwm at 110b0000 { > + compatible = "rockchip,rk3288-pwm"; > + reg = <0x110b0000 0x10>; > + #pwm-cells = <3>; @@ -289,7 +289,7 @@ the controller. > + status = "disabled"; > + }; > + -> + pwm1: pwm@110b0010 { +> + pwm1: pwm at 110b0010 { > + compatible = "rockchip,rk3288-pwm"; > + reg = <0x110b0010 0x10>; > + #pwm-cells = <3>; @@ -300,7 +300,7 @@ the controller. > + status = "disabled"; > + }; > + -> + pwm2: pwm@110b0020 { +> + pwm2: pwm at 110b0020 { > + compatible = "rockchip,rk3288-pwm"; > + reg = <0x110b0020 0x10>; > + #pwm-cells = <3>; @@ -311,7 +311,7 @@ the controller. > + status = "disabled"; > + }; > + -> + pwm3: pwm@110b0030 { +> + pwm3: pwm at 110b0030 { > + compatible = "rockchip,rk3288-pwm"; > + reg = <0x110b0030 0x10>; > + #pwm-cells = <2>; @@ -322,7 +322,7 @@ the controller. > + status = "disabled"; > + }; > + -> + uart0: serial@11010000 { +> + uart0: serial at 11010000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x11010000 0x100>; > + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; @@ -336,7 +336,7 @@ the controller. > + status = "disabled"; > + }; > + -> + uart1: serial@11020000 { +> + uart1: serial at 11020000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x11020000 0x100>; > + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; @@ -350,7 +350,7 @@ the controller. > + status = "disabled"; > + }; > + -> + uart2: serial@11030000 { +> + uart2: serial at 11030000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x11030000 0x100>; > + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; @@ -372,7 +372,7 @@ the controller. > + #size-cells = <1>; > + ranges; > + -> + gpio0: gpio0@11110000 { +> + gpio0: gpio0 at 11110000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x11110000 0x100>; > + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; @@ -385,7 +385,7 @@ the controller. > + #interrupt-cells = <2>; > + }; > + -> + gpio1: gpio1@11120000 { +> + gpio1: gpio1 at 11120000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x11120000 0x100>; > + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; @@ -398,7 +398,7 @@ the controller. > + #interrupt-cells = <2>; > + }; > + -> + gpio2: gpio2@11130000 { +> + gpio2: gpio2 at 11130000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x11130000 0x100>; > + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; @@ -411,7 +411,7 @@ the controller. > + #interrupt-cells = <2>; > + }; > + -> + gpio3: gpio3@11140000 { +> + gpio3: gpio3 at 11140000 { > + compatible = "rockchip,gpio-bank"; > + reg = <0x11140000 0x100>; > + interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; diff --git a/a/content_digest b/N1/content_digest index 9326d83..c8ea350 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,19 +1,9 @@ "ref\01449651853-1667-1-git-send-email-jeffy.chen@rock-chips.com\0" "ref\01449651853-1667-8-git-send-email-jeffy.chen@rock-chips.com\0" - "From\0Heiko Stuebner <heiko@sntech.de>\0" - "Subject\0Re: [PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi\0" + "From\0heiko@sntech.de (Heiko Stuebner)\0" + "Subject\0[PATCH v1 7/8] ARM: dts: rockchip: add core rk3228 dtsi\0" "Date\0Thu, 10 Dec 2015 01:32:03 +0100\0" - "To\0Jeffy Chen <jeffy.chen@rock-chips.com>\0" - "Cc\0linux@arm.linux.org.uk" - linux-arm-kernel@lists.infradead.org - linux-rockchip@lists.infradead.org - linux-kernel@vger.kernel.org - devicetree@vger.kernel.org - Kumar Gala <galak@codeaurora.org> - Ian Campbell <ijc+devicetree@hellion.org.uk> - Rob Herring <robh+dt@kernel.org> - Pawel Moll <pawel.moll@arm.com> - " Mark Rutland <mark.rutland@arm.com>\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Jeffy,\n" @@ -110,7 +100,7 @@ "\"rockchip,rk3036-smp\" work for you?\n" "\n" "> +\n" - "> +\t\tcpu0: cpu@f00 {\n" + "> +\t\tcpu0: cpu at f00 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\treg = <0xf00>;\n" @@ -123,21 +113,21 @@ "> +\t\t\tclocks = <&cru ARMCLK>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu1: cpu@f01 {\n" + "> +\t\tcpu1: cpu at f01 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\treg = <0xf01>;\n" "> +\t\t\tresets = <&cru SRST_CORE1>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu2: cpu@f02 {\n" + "> +\t\tcpu2: cpu at f02 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\treg = <0xf02>;\n" "> +\t\t\tresets = <&cru SRST_CORE2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tcpu3: cpu@f03 {\n" + "> +\t\tcpu3: cpu at f03 {\n" "> +\t\t\tdevice_type = \"cpu\";\n" "> +\t\t\tcompatible = \"arm,cortex-a7\";\n" "> +\t\t\treg = <0xf03>;\n" @@ -151,7 +141,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tpdma: pdma@110f0000 {\n" + "> +\t\tpdma: pdma at 110f0000 {\n" "> +\t\t\tcompatible = \"arm,pl330\", \"arm,primecell\";\n" "> +\t\t\treg = <0x110f0000 0x4000>;\n" "> +\t\t\tinterrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,\n" @@ -226,7 +216,7 @@ "> +\t\t#clock-cells = <0>;\n" "> +\t};\n" "> +\n" - "> +\tcru: clock-controller@110e0000 {\n" + "> +\tcru: clock-controller at 110e0000 {\n" "> +\t\tcompatible = \"rockchip,rk3228-cru\";\n" "> +\t\treg = <0x110e0000 0x1000>;\n" "> +\t\trockchip,grf = <&grf>;\n" @@ -236,7 +226,7 @@ "> +\t\tassigned-clock-rates = <594000000>;\n" "> +\t};\n" "> +\n" - "> +\tgic: interrupt-controller@32010000 {\n" + "> +\tgic: interrupt-controller at 32010000 {\n" "\n" "please order by register address, so gic should move quite\n" "a bit lower.\n" @@ -254,12 +244,12 @@ "\n" "> +\t};\n" "> +\n" - "> +\tgrf: syscon@11000000 {\n" + "> +\tgrf: syscon at 11000000 {\n" "> +\t\tcompatible = \"syscon\";\n" "> +\t\treg = <0x11000000 0x1000>;\n" "> +\t};\n" "> +\n" - "> +\ttimer: timer@110c0000 {\n" + "> +\ttimer: timer at 110c0000 {\n" "> +\t\tcompatible = \"rockchip,rk3288-timer\";\n" "> +\t\treg = <0x110c0000 0x20>;\n" "> +\t\tinterrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -267,7 +257,7 @@ "> +\t\tclock-names = \"timer\", \"pclk\";\n" "> +\t};\n" "> +\n" - "> +\temmc: dwmmc@30020000 {\n" + "> +\temmc: dwmmc at 30020000 {\n" "> +\t\tcompatible = \"rockchip,rk3288-dw-mshc\";\n" "> +\t\tclock-frequency = <37500000>;\n" "> +\t\tclock-freq-min-max = <400000 37500000>;\n" @@ -296,7 +286,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tpwm0: pwm@110b0000 {\n" + "> +\tpwm0: pwm at 110b0000 {\n" "> +\t\tcompatible = \"rockchip,rk3288-pwm\";\n" "> +\t\treg = <0x110b0000 0x10>;\n" "> +\t\t#pwm-cells = <3>;\n" @@ -307,7 +297,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tpwm1: pwm@110b0010 {\n" + "> +\tpwm1: pwm at 110b0010 {\n" "> +\t\tcompatible = \"rockchip,rk3288-pwm\";\n" "> +\t\treg = <0x110b0010 0x10>;\n" "> +\t\t#pwm-cells = <3>;\n" @@ -318,7 +308,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tpwm2: pwm@110b0020 {\n" + "> +\tpwm2: pwm at 110b0020 {\n" "> +\t\tcompatible = \"rockchip,rk3288-pwm\";\n" "> +\t\treg = <0x110b0020 0x10>;\n" "> +\t\t#pwm-cells = <3>;\n" @@ -329,7 +319,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tpwm3: pwm@110b0030 {\n" + "> +\tpwm3: pwm at 110b0030 {\n" "> +\t\tcompatible = \"rockchip,rk3288-pwm\";\n" "> +\t\treg = <0x110b0030 0x10>;\n" "> +\t\t#pwm-cells = <2>;\n" @@ -340,7 +330,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tuart0: serial@11010000 {\n" + "> +\tuart0: serial at 11010000 {\n" "> +\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\treg = <0x11010000 0x100>;\n" "> +\t\tinterrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -354,7 +344,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tuart1: serial@11020000 {\n" + "> +\tuart1: serial at 11020000 {\n" "> +\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\treg = <0x11020000 0x100>;\n" "> +\t\tinterrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -368,7 +358,7 @@ "> +\t\tstatus = \"disabled\";\n" "> +\t};\n" "> +\n" - "> +\tuart2: serial@11030000 {\n" + "> +\tuart2: serial at 11030000 {\n" "> +\t\tcompatible = \"snps,dw-apb-uart\";\n" "> +\t\treg = <0x11030000 0x100>;\n" "> +\t\tinterrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -390,7 +380,7 @@ "> +\t\t#size-cells = <1>;\n" "> +\t\tranges;\n" "> +\n" - "> +\t\tgpio0: gpio0@11110000 {\n" + "> +\t\tgpio0: gpio0 at 11110000 {\n" "> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "> +\t\t\treg = <0x11110000 0x100>;\n" "> +\t\t\tinterrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -403,7 +393,7 @@ "> +\t\t\t#interrupt-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio1: gpio1@11120000 {\n" + "> +\t\tgpio1: gpio1 at 11120000 {\n" "> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "> +\t\t\treg = <0x11120000 0x100>;\n" "> +\t\t\tinterrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -416,7 +406,7 @@ "> +\t\t\t#interrupt-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio2: gpio2@11130000 {\n" + "> +\t\tgpio2: gpio2 at 11130000 {\n" "> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "> +\t\t\treg = <0x11130000 0x100>;\n" "> +\t\t\tinterrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -429,7 +419,7 @@ "> +\t\t\t#interrupt-cells = <2>;\n" "> +\t\t};\n" "> +\n" - "> +\t\tgpio3: gpio3@11140000 {\n" + "> +\t\tgpio3: gpio3 at 11140000 {\n" "> +\t\t\tcompatible = \"rockchip,gpio-bank\";\n" "> +\t\t\treg = <0x11140000 0x100>;\n" "> +\t\t\tinterrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -547,4 +537,4 @@ "> +};\n" > -e87608ad2552d50bbe058286a6f9f99ff2540f3e4911541f9d171f042c38a8be +80921fb7560f2cf5d675539ae3cd13979317d7df6dea54d76d379a2c042597f4
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