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Date: Sat, 25 Feb 2006 02:58:09 -0800
From: "Sewook Wee" <weese@stanford.edu>
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Subject: Data Cache Write Through
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Hello all,

I am Sewook Wee at Stanford University.
For the research purpose, I am hacking the linux kernel (version 2.4.30) fo=
r
The PPC405 in Virtex II Pro Xilinx FPGA.
What I want to do is make Data Cache policy to be write-through, not
write-back.
I changed the DCWR Value in the arch/ppc/mm/44x_mmu.c, but seems it does no=
t
work.

I hope some of you have decent idea to make it happen.

Thanks.



--
Sewook Wee
  weese@stanford.edu
  Computer System Laboratory
  Stanford University

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<div>Hello all, </div>
<div>&nbsp;</div>
<div>I am Sewook Wee at Stanford University.</div>
<div>For the research purpose, I am hacking the linux kernel (version 2.4.3=
0) for The PPC405 in Virtex II Pro Xilinx FPGA. </div>
<div>What I want to do is make Data Cache policy to be write-through, not w=
rite-back.</div>
<div>I changed the DCWR Value in the arch/ppc/mm/44x_mmu.c, but seems it do=
es not work. </div>
<div>&nbsp;</div>
<div>I hope some of you have decent idea to make it happen.</div>
<div>&nbsp;</div>
<div>Thanks.</div>
<div>&nbsp;</div><br clear=3D"all"><br>-- <br>Sewook Wee<br>&nbsp;&nbsp;<a =
href=3D"mailto:weese@stanford.edu">weese@stanford.edu</a><br>&nbsp;&nbsp;Co=
mputer System Laboratory <br>&nbsp;&nbsp;Stanford University=20

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