From mboxrd@z Thu Jan 1 00:00:00 1970 From: Murray.Jensen at csiro.au Date: Fri, 15 Jul 2005 10:40:53 +1000 Subject: [U-Boot-Users] [id]cache_status looks at wrong bit for MPC8560 Message-ID: <2574.1121388053@gerd> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi, the [id]cache_status functions in the MPC85xx start.S code look at the wrong bit in the L1CSRn registers for the MPC8560. I have a patch for it, but I was wondering if the code is wrong for all 85xx processors, or just the 8560. Rather than me downloading all the 85xx user manuals and checking the register bits (as I am only interested in 8560) I thought I would post here instead. If anyone knows for certain the code is correct or otherwise for other 85xx processors, please let me know. Cheers! Murray... -- Murray Jensen, CSIRO Manufacturing & Infra. Tech. Phone: +61 3 9662 7763 Locked Bag No. 9, Preston, Vic, 3072, Australia. Fax: +61 3 9662 7853 Internet: Murray.Jensen at csiro.au To the extent permitted by law, CSIRO does not represent, warrant and/or guarantee that the integrity of this communication has been maintained or that the communication is free of errors, virus, interception or interference. The information contained in this e-mail may be confidential or privileged. Any unauthorised use or disclosure is prohibited. If you have received this e-mail in error, please delete it immediately and notify Murray Jensen on +61 3 9662 7763. Thank you.