Re: [PATCH v5 3/3] perf x86: Exposing an Uncore unit to PMON for Intel Xeon® server platform

["Liang, Kan" <kan.liang@linux.intel.com>]

On 2/11/2020 1:57 PM, Greg KH wrote:
> On Tue, Feb 11, 2020 at 10:42:00AM -0800, Andi Kleen wrote:
>> On Tue, Feb 11, 2020 at 09:15:44AM -0800, Greg KH wrote:
>>> On Tue, Feb 11, 2020 at 07:15:49PM +0300, roman.sudarikov@linux.intel.com wrote:
>>>> +static ssize_t skx_iio_mapping_show(struct device *dev,
>>>> +				struct device_attribute *attr, char *buf)
>>>> +{
>>>> +	struct pmu *pmu = dev_get_drvdata(dev);
>>>> +	struct intel_uncore_pmu *uncore_pmu =
>>>> +		container_of(pmu, struct intel_uncore_pmu, pmu);
>>>> +
>>>> +	struct dev_ext_attribute *ea =
>>>> +		container_of(attr, struct dev_ext_attribute, attr);
>>>> +	long die = (long)ea->var;
>>>> +
>>>> +	return sprintf(buf, "0000:%02x\n", skx_iio_stack(uncore_pmu, die));
>>>
>>> If "0000:" is always the "prefix" of the output of this file, why have
>>> it at all as you always know it is there?


I think Roman only test with BIOS configured as single-segment. So he 
hard-code the segment# here.

I'm not sure if Roman can do some test with multiple-segment BIOS. If 
not, I think we should at least print a warning here.

>>>
>>> What is ever going to cause that to change?
>>
>> I think it's just to make it a complete PCI address.
> 
> Is that what this really is?  If so, it's not a "complete" pci address,
> is it?  If it is, use the real pci address please.

I think we don't need a complete PCI address here. The attr is to 
disclose the mapping information between die and PCI BUS. Segment:BUS 
should be good enough.

Thanks,
Kan

> 
>> In theory it might be different on a complex multi node system with
>> custom interconnect and multiple PCI segments, but that would need code
>> changes too.
>>
>> This version of the patchkit only supports standard SKX systems
>> at this point.
> 
> I have no idea what that means, please translate for non-Intel people :)
> 
> greg k-h
>