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Fri, 21 Aug 2026 21:32:05 +0000 Message-ID: <266cab79-8978-4c18-aee5-e576a9d3fd46@amd.com> Date: Fri, 21 Aug 2026 16:32:02 -0500 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/3] drm/amdgpu/userq: create the same workaround of oversubscription timer Content-Language: en-US To: Eric Huang , amd-gfx@lists.freedesktop.org Cc: Tishko.Araz@amd.com, Alexander.Deucher@amd.com References: <20260819201443.282689-1-jinhuieric.huang@amd.com> <20260819201443.282689-3-jinhuieric.huang@amd.com> From: Mario Limonciello In-Reply-To: <20260819201443.282689-3-jinhuieric.huang@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: DS1PR06CA0001.namprd06.prod.outlook.com (2603:10b6:8:458::11) To PH8PR12MB6914.namprd12.prod.outlook.com (2603:10b6:510:1cb::21) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH8PR12MB6914:EE_|CH3PR12MB8536:EE_ X-MS-Office365-Filtering-Correlation-Id: bcb794d1-6d1a-4be7-8d4d-08deffcba515 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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> } > > +static void amdgpu_mes_userq_notify_unmap_work_handler(struct work_struct *work); > + > int amdgpu_mes_init(struct amdgpu_device *adev) > { > int i, r, num_pipes, num_queues = 0; > @@ -123,6 +125,9 @@ int amdgpu_mes_init(struct amdgpu_device *adev) > spin_lock_init(&adev->mes.ring_lock[i]); > > adev->mes.total_max_queue = AMDGPU_FENCE_MES_QUEUE_ID_MASK; > + atomic_set(&adev->mes.userq_hw_queue_count, 0); > + INIT_DELAYED_WORK(&adev->mes.userq_notify_unmap_work, > + amdgpu_mes_userq_notify_unmap_work_handler); > total_vmid_mask = (u32)((1UL << 16) - 1); > reserved_vmid_mask = (u32)((1UL << adev->vm_manager.first_kfd_vmid) - 1); > > @@ -288,6 +293,8 @@ void amdgpu_mes_fini(struct amdgpu_device *adev) > int i; > int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; > > + cancel_delayed_work_sync(&adev->mes.userq_notify_unmap_work); > + > kfree(adev->gfx.mec.mes_hung_db_array); > > amdgpu_bo_free_kernel(&adev->mes.event_log_gpu_obj, > @@ -1163,6 +1170,69 @@ int amdgpu_mes_notify_unmap_queue(struct amdgpu_device *adev) > return r; > } > > +/* Interval for notifying MES of work on unmapped queues during oversubscription */ > +#define AMDGPU_USERQ_UNMAP_NOTIFY_DELAY_MS 50 > + > +static unsigned int amdgpu_mes_userq_hw_queue_num(struct amdgpu_device *adev) > +{ > + int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1; > + unsigned int n = bitmap_weight(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES); > + int i; > + > + for (i = 0; i < num_xcc; i++) > + n += bitmap_weight(adev->gfx.mec_bitmap[i].queue_bitmap, > + AMDGPU_MAX_COMPUTE_QUEUES); > + > + return n; > +} > + > +static void amdgpu_mes_userq_notify_unmap_work_handler(struct work_struct *work) > +{ > + struct amdgpu_mes *mes = container_of(work, struct amdgpu_mes, > + userq_notify_unmap_work.work); > + struct amdgpu_device *adev = mes->adev; > + > + amdgpu_mes_notify_unmap_queue(adev); > + > + /* Re-arm if still oversubscribed */ > + if (atomic_read(&mes->userq_hw_queue_count) > > + amdgpu_mes_userq_hw_queue_num(adev)) > + queue_delayed_work(system_wq, &mes->userq_notify_unmap_work, > + msecs_to_jiffies(AMDGPU_USERQ_UNMAP_NOTIFY_DELAY_MS)); > +} > + > +/* > + * Called after a GFX11 usermode queue is successfully mapped to MES. > + * Starts the periodic unmap-notify timer if this pushed the device into > + * HW queue oversubscription. > + */ > +void amdgpu_mes_userq_queue_mapped(struct amdgpu_device *adev) > +{ > + if (!(amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && > + amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0))) > + return; > + > + if (atomic_inc_return(&adev->mes.userq_hw_queue_count) > > + amdgpu_mes_userq_hw_queue_num(adev)) > + queue_delayed_work(system_wq, &adev->mes.userq_notify_unmap_work, > + msecs_to_jiffies(AMDGPU_USERQ_UNMAP_NOTIFY_DELAY_MS)); > +} > + > +/* > + * Called after a GFX11 usermode queue is unmapped from MES. Stops the > + * periodic unmap-notify timer once oversubscription clears. > + */ > +void amdgpu_mes_userq_queue_unmapped(struct amdgpu_device *adev) > +{ > + if (!(amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0) && > + amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(12, 0, 0))) > + return; > + > + if (atomic_dec_return(&adev->mes.userq_hw_queue_count) <= > + amdgpu_mes_userq_hw_queue_num(adev)) > + cancel_delayed_work(&adev->mes.userq_notify_unmap_work); > +} > + > #if defined(CONFIG_DEBUG_FS) > > static int amdgpu_debugfs_mes_event_log_show(struct seq_file *m, void *unused) > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h > index 0291ae14a1e7..5160b227943b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h > @@ -29,6 +29,7 @@ > #include "amdgpu_gfx.h" > #include "amdgpu_doorbell.h" > #include > +#include > > #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 > #define AMDGPU_MES_MAX_GFX_PIPES 2 > @@ -90,6 +91,10 @@ struct amdgpu_mes { > uint32_t total_max_queue; > uint32_t max_doorbell_slices; > > + /* GFX11 usermode queue oversubscription notify timer */ > + atomic_t userq_hw_queue_count; > + struct delayed_work userq_notify_unmap_work; > + > uint64_t default_process_quantum; > uint64_t default_gang_quantum; > > @@ -646,5 +651,7 @@ void amdgpu_mes_free_gang_ctx_index(struct amdgpu_mes *mes, > uint32_t index); > > int amdgpu_mes_notify_unmap_queue(struct amdgpu_device *adev); > +void amdgpu_mes_userq_queue_mapped(struct amdgpu_device *adev); > +void amdgpu_mes_userq_queue_unmapped(struct amdgpu_device *adev); > > #endif /* __AMDGPU_MES_H__ */ > diff --git a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c > index fae709f134bb..5a10af16e0c1 100644 > --- a/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c > +++ b/drivers/gpu/drm/amd/amdgpu/mes_userqueue.c > @@ -171,6 +171,8 @@ static int mes_userq_map(struct amdgpu_usermode_queue *queue) > return r; > } > > + amdgpu_mes_userq_queue_mapped(adev); > + > DRM_DEBUG_DRIVER("Queue (doorbell:%d) mapped successfully\n", userq_props->doorbell_index); > return 0; > } > @@ -195,9 +197,13 @@ static int mes_userq_unmap(struct amdgpu_usermode_queue *queue) > amdgpu_mes_unlock(&adev->mes); > if (mes->use_rs64mem) > amdgpu_mes_free_gang_ctx_index(mes, queue->gang_ctx_array_index); > - if (r) > + if (r) { > DRM_ERROR("Failed to unmap queue in HW, err (%d)\n", r); > - return r; > + return r; > + } > + > + amdgpu_mes_userq_queue_unmapped(adev); > + return 0; > } > > int mes_userq_reset(struct amdgpu_usermode_queue *queue)