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Thu, 26 Dec 2024 04:52:03 -0800 (PST) Received: from [192.168.68.110] ([187.101.65.72]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-72aad8dbbabsm13294859b3a.101.2024.12.26.04.52.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 26 Dec 2024 04:52:03 -0800 (PST) Message-ID: <26ecf1ca-07eb-4aed-9d06-a12c036c0723@ventanamicro.com> Date: Thu, 26 Dec 2024 09:51:59 -0300 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 5/7] target/riscv: Add Smrnmi cpu extension To: frank.chang@sifive.com, qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Liu Zhiwei , Tommy Wu References: <20241217062440.884261-1-frank.chang@sifive.com> <20241217062440.884261-6-frank.chang@sifive.com> Content-Language: en-US From: Daniel Henrique Barboza In-Reply-To: <20241217062440.884261-6-frank.chang@sifive.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-riscv@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Sender: qemu-riscv-bounces+qemu-riscv=archiver.kernel.org@nongnu.org Frank, I believe patch 7 should be squashed in with this one. This patch will break 'check-functional' because the 'max' CPU isn't able to support Smrnmi and we're only fixing it 2 patches later. In theory this is fine but it can be problematic when doing bisecting looking for bugs. If you merge patch 7 with this patch please also add: Reviewed-by: Daniel Henrique Barboza Thanks, Daniel On 12/17/24 3:24 AM, frank.chang@sifive.com wrote: > From: Tommy Wu > > This adds the properties for ISA extension Smrnmi. > > Signed-off-by: Frank Chang > Signed-off-by: Tommy Wu > --- > target/riscv/cpu.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index e6988f44c6..7a4aa235ce 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -193,6 +193,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), > + ISA_EXT_DATA_ENTRY(smrnmi, PRIV_VERSION_1_12_0, ext_smrnmi), > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), > @@ -1621,6 +1622,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > > MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false), > MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false), > + MULTI_EXT_CFG_BOOL("smrnmi", ext_smrnmi, false), > MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), > MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false), > MULTI_EXT_CFG_BOOL("svade", ext_svade, false),