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envelope-from=philmd@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-arm@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org Sender: qemu-arm-bounces+qemu-arm=archiver.kernel.org@nongnu.org On 2026-10-19 4:44, Jamin Lin wrote: > Setting msi_nonbroken in class_init() affects all machine types, > even when the ASPEED PCIe controller is not used. > > Move msi_nonbroken to realize() to ensure it is only set when > the ASPEED PCIe controller is realized. > > Reported-by: Marcelo Manzo > Fixes: f002aa35f3205d55bbe4a68670ba19a6dcf1d6a8 ("hw/pci-host/aspeed: Add AST2600 PCIe config space and host bridge") This commit mentions AST2600 but also enable that for AST2400/2500 and AST2700. AST2700 wires it in commit ba6fb09048198a2952d731cd063f4307b137e7ec. AST2400/2500 share hw/arm/aspeed_ast2400.c which has no PCIe host bridge. Previous commits could have been better, but too late, OK. Suggestion: The ASPEED PCIe class may be registered for machines that do not instantiate a PCIe root complex. Updating the global msi_nonbroken flag from class_init() therefore affects unrelated machines. Defer the update to the per-device realize handler, so the flag changes only when an ASPEED PCIe root complex is actually instantiated. Fixes: f002aa35f3 ("hw/pci-host/aspeed: Add AST2600 PCIe host bridge") Reviewed-by: Philippe Mathieu-Daudé > Signed-off-by: Jamin Lin > --- > hw/pci-host/aspeed_pcie.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-)