From mboxrd@z Thu Jan 1 00:00:00 1970 From: Thomas Monjalon Subject: Re: [PATCH] config: set cache line as 128B in the generic arm64 config Date: Sun, 30 Apr 2017 23:10:16 +0200 Message-ID: <2751948.JIQzdyJ0NR@xps> References: <20170426162919.15397-1-jerin.jacob@caviumnetworks.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Cc: dev@dpdk.org, Jianbo Liu , Hemant Agrawal , christian.ehrhardt@canonical.com To: Jerin Jacob Return-path: Received: from out4-smtp.messagingengine.com (out4-smtp.messagingengine.com [66.111.4.28]) by dpdk.org (Postfix) with ESMTP id 77A7F7C97 for ; Sun, 30 Apr 2017 23:10:19 +0200 (CEST) In-Reply-To: List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" 28/04/2017 04:14, Jianbo Liu: > On 27 April 2017 at 00:29, Jerin Jacob wrote: > > armv8 implementations may have 64B or 128B cache line. > > Setting to the maximum available cache line size in generic config to > > address minimum DMA alignment across all arm64 implementations. > > > > Increasing the cacheline size has no negative impact to cache invalidation > > on systems with a smaller cache line. > > > > The need for the minimum DMA alignment has impact on functional aspects > > of the platform so default config should cater the functional aspects. > > > > There is an impact on memory usage with this scheme, but that's not too > > important for the single image arm64 distribution use case. > > > > The arm64 linux kernel followed the similar approach for single > > arm64 image use case. > > http://lxr.free-electrons.com/source/arch/arm64/include/asm/cache.h > > > > Signed-off-by: Jerin Jacob > > Acked-by: Jianbo Liu Applied, thanks