From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH 2/2] agp/intel: Use a write-combining map for updating PTEs Date: Fri, 14 Sep 2012 12:08:06 +0100 Message-ID: <275ffc$6jn85r@fmsmga002.fm.intel.com> References: <1347620267-11275-1-git-send-email-chris@chris-wilson.co.uk> <1347620267-11275-2-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id 5E5DEA0FD0 for ; Fri, 14 Sep 2012 04:08:22 -0700 (PDT) In-Reply-To: <1347620267-11275-2-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, 14 Sep 2012 11:57:47 +0100, Chris Wilson wrote: > v2: Limit the WC mapping to older generations as we should the TLB > invalidation on SandyBridge+ unreliable. /me fires his editor and proof-reader v2: Limit the WC mapping to older generations as we have observed that the TLB invalidation on SandyBridge+ is unreliable with WC updates. See i-g-t/tests/gem_gtt_cpu_tlb -Chris -- Chris Wilson, Intel Open Source Technology Centre