From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm: micro optimise cache flushing Date: Wed, 19 Sep 2012 08:50:18 +0100 Message-ID: <275ffc$6li573@fmsmga002.fm.intel.com> References: <1348017161-27475-1-git-send-email-airlied@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id AC1689EB76 for ; Wed, 19 Sep 2012 00:50:40 -0700 (PDT) In-Reply-To: <1348017161-27475-1-git-send-email-airlied@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org Errors-To: dri-devel-bounces+sf-dri-devel=m.gmane.org@lists.freedesktop.org To: Dave Airlie , dri-devel@lists.freedesktop.org List-Id: dri-devel@lists.freedesktop.org On Wed, 19 Sep 2012 11:12:41 +1000, Dave Airlie wrote: > From: Dave Airlie > > We hit this a lot with i915 and although we'd like to engineer things to hit > it a lot less, this commit at least makes it consume a few less cycles. > > from something containing > movzwl 0x0(%rip),%r10d > to > add %r8,%rdx > > I only noticed it while using perf to profile something else. > > Signed-off-by: Dave Airlie Reviewed-by: Chris Wilson I would have thought this is something the compiler should, with the appropriate hints, be smart enough to decide for itself as boot_cpu_data should be constant once defined. *shrug* -Chris -- Chris Wilson, Intel Open Source Technology Centre